]>
Commit | Line | Data |
---|---|---|
ffba35f8 MG |
1 | PROJ = master |
2 | PIN_DEF = master.pcf | |
a051754e MG |
3 | DEVICE = hx1k |
4 | ||
5 | all: $(PROJ).rpt $(PROJ).bin | |
6 | ||
7 | %.blif: %.v | |
ffba35f8 | 8 | tools/yosys/yosys -p 'synth_ice40 -top master -blif $@' $< |
a051754e MG |
9 | |
10 | %.asc: $(PIN_DEF) %.blif | |
2ed306f8 | 11 | tools/arachne-pnr/bin/arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^ -P tq144 |
a051754e MG |
12 | |
13 | %.bin: %.asc | |
2ed306f8 | 14 | tools/icestorm/icepack/icepack $< $@ |
a051754e MG |
15 | |
16 | %.rpt: %.asc | |
7560fdba | 17 | tools/icestorm/icetime/icetime -C tools/icestorm/icebox/chipdb-$(subst hx,,$(subst lp,,$(DEVICE))).txt -d $(DEVICE) -mtr $@ $< |
a051754e MG |
18 | |
19 | prog: $(PROJ).bin | |
2ed306f8 | 20 | tools/icestorm/iceprog/iceprog $< |
a051754e MG |
21 | |
22 | clean: | |
23 | rm -f $(PROJ).blif $(PROJ).asc $(PROJ).bin | |
24 | ||
23c26e04 MG |
25 | |
26 | sim: | |
ffba35f8 | 27 | tools/yosys/yosys -p 'read_verilog -sv -DSIM master.v; prep -top master -nordff; sim -clock CLKin -vcd test.vcd -n 3000' |
23c26e04 MG |
28 | |
29 | .PHONY: all prog clean sim |