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08f23977 MG |
1 | `define STATE_READ 3'b100 |
2 | `define STATE_RUN 3'b010 | |
3 | `define STATE_WRITE 3'b001 | |
4 | ||
5 | `ifdef SIM | |
6 | `define START_STATE `STATE_RUN | |
7 | `else | |
8 | `define START_STATE `STATE_READ | |
9 | `endif | |
10 | ||
11 | module CTRL (input clk, input step_eval, input reader_finished, input eval_finished, input writer_finished, output gc_clock_enable, output eval_clock_enable, output reader_clock_enable, output writer_clock_enable, output reset, input gc_ram_we, input reader_ram_we, input [12:0] gc_ram_addr, input [12:0] reader_ram_addr, input [12:0] writer_ram_addr, input [15:0] gc_ram_di, input [15:0] reader_ram_di, output ram_we, output [12:0] ram_addr, output [15:0] ram_di, input uart_is_receiving, input uart_is_transmitting, output [4:0] led); | |
12 | reg [3:0] state = `START_STATE; | |
13 | ||
14 | wire is_reading = state == `STATE_READ; | |
15 | wire is_running = state == `STATE_RUN; | |
16 | wire is_writing = state == `STATE_WRITE; | |
17 | ||
18 | assign gc_clock_enable = is_running; | |
19 | assign eval_clock_enable = step_eval & is_running; | |
20 | assign reader_clock_enable = is_reading; | |
21 | assign writer_clock_enable = is_writing; | |
22 | assign reset = !is_running; | |
23 | ||
24 | always @ (posedge clk) begin | |
25 | if(is_writing & writer_finished) | |
26 | state <= `STATE_READ; | |
27 | ||
28 | if(is_reading & reader_finished) | |
29 | state <= `STATE_RUN; | |
30 | ||
31 | if(is_running & eval_finished) | |
32 | state <= `STATE_WRITE; | |
33 | end | |
34 | ||
35 | assign ram_we = reader_clock_enable ? reader_ram_we : gc_ram_we; | |
36 | assign ram_addr = reader_clock_enable ? reader_ram_addr : writer_clock_enable ? writer_ram_addr : gc_ram_addr; | |
37 | assign ram_di = reader_clock_enable ? reader_ram_di : gc_ram_di; | |
38 | ||
39 | assign led[0] = is_reading; | |
40 | assign led[1] = uart_is_receiving; | |
41 | assign led[2] = is_writing; | |
42 | assign led[3] = uart_is_transmitting; | |
43 | assign led[4] = is_running; | |
44 | endmodule |