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1`define OP_NOP 3'd0
2`define OP_LOADA 3'd1
3`define OP_LOADB 3'd2
4`define OP_STORE 3'd3
5`define OP_READ 3'd4
6`define OP_LOADI 3'd5
7`define OP_ROUTE 3'd6
8`define OP_RUG 3'd7
9
10`define DIRECTION_N 3'd0
11`define DIRECTION_NE 3'd1
12`define DIRECTION_E 3'd2
13`define DIRECTION_SE 3'd3
14`define DIRECTION_S 3'd4
15`define DIRECTION_SW 3'd5
16`define DIRECTION_W 3'd6
17`define DIRECTION_NW 3'd7
18
19module chip(input clk, input [2:0] op, input [15:0] I, input io_pin, input CS, output reg [15:0] mem_in, input [15:0] mem_out, output reg mem_write);
20
21 // parity is unimplemented
22
23 // OP_LOADA
24 wire [3:0] flagr = I[3:0];
25 wire bsel = I[4];
26 wire [0:7] aluc = I[12:5];
27
28 // OP_LOADB
29 wire [3:0] cond = I[3:0];
30 wire inv = I[4];
31 wire [0:7] alus = I[12:5];
32
33 // OP_STORE
34 wire [3:0] flagw = I[3:0];
35 wire edge_ = I[7];
36 wire [3:0] cube = I[11:8];
37
38 // OP_ROUTE
39 wire [5:0] cycle = I[5:0];
40 wire [1:0] check = I[7:6];
41 wire [3:0] xor_ = I[11:8];
42 wire [2:0] snarf = I[14:12];
43 wire odd = I[15];
44
45 // OP_RUG
46 wire rw = I[0];
47 wire ac = I[1];
48 wire news = I[2];
49 wire [4:0] reg_ = I[8:4];
50
51
52 reg [15:0] A = 0;
53 reg [15:0] B = 0;
54 reg [15:0] C = 0;
55 reg [15:0] F = 0;
56 reg [15:0] Cond = 0;
57 reg [15:0] R = 0;
58 reg [7:0] alu_sum = 0;
59 reg [7:0] alu_carry = 0;
60 reg [15:0] cube_in;
61 reg io;
62
63 // these are not really regs
64
65 reg [15:0] alu_sum_out;
66 reg [15:0] alu_carry_out;
67
68 reg [2:0] alu_index [15:0];
69
70 reg [15:0] idx;
71
72 always @* begin
73 for(idx = 0; idx < 16; idx=idx+1) begin
74 alu_index[idx] = (A[idx] << 2) + (B[idx] << 1) + F[idx];
75 alu_sum_out[idx] <= alu_sum[alu_index[idx]];
76 alu_carry_out[idx] <= alu_carry[alu_index[idx]];
77 end
78 end
79
80 reg [3:0] newstable[0:15][0:7];
81
82 initial begin
83 newstable[0][0] = 12;
84 newstable[0][1] = 13;
85 newstable[0][2] = 1;
86 newstable[0][3] = 5;
87 newstable[0][4] = 4;
88 newstable[0][5] = 7;
89 newstable[0][6] = 3;
90 newstable[0][7] = 15;
91 newstable[1][0] = 13;
92 newstable[1][1] = 14;
93 newstable[1][2] = 2;
94 newstable[1][3] = 6;
95 newstable[1][4] = 5;
96 newstable[1][5] = 4;
97 newstable[1][6] = 0;
98 newstable[1][7] = 12;
99 newstable[2][0] = 14;
100 newstable[2][1] = 15;
101 newstable[2][2] = 3;
102 newstable[2][3] = 7;
103 newstable[2][4] = 6;
104 newstable[2][5] = 5;
105 newstable[2][6] = 1;
106 newstable[2][7] = 13;
107 newstable[3][0] = 15;
108 newstable[3][1] = 12;
109 newstable[3][2] = 0;
110 newstable[3][3] = 4;
111 newstable[3][4] = 7;
112 newstable[3][5] = 6;
113 newstable[3][6] = 2;
114 newstable[3][7] = 14;
115 newstable[4][0] = 0;
116 newstable[4][1] = 1;
117 newstable[4][2] = 5;
118 newstable[4][3] = 9;
119 newstable[4][4] = 8;
120 newstable[4][5] = 11;
121 newstable[4][6] = 7;
122 newstable[4][7] = 3;
123 newstable[5][0] = 1;
124 newstable[5][1] = 2;
125 newstable[5][2] = 6;
126 newstable[5][3] = 10;
127 newstable[5][4] = 9;
128 newstable[5][5] = 8;
129 newstable[5][6] = 4;
130 newstable[5][7] = 0;
131 newstable[6][0] = 2;
132 newstable[6][1] = 3;
133 newstable[6][2] = 7;
134 newstable[6][3] = 11;
135 newstable[6][4] = 10;
136 newstable[6][5] = 9;
137 newstable[6][6] = 5;
138 newstable[6][7] = 1;
139 newstable[7][0] = 3;
140 newstable[7][1] = 0;
141 newstable[7][2] = 4;
142 newstable[7][3] = 8;
143 newstable[7][4] = 11;
144 newstable[7][5] = 10;
145 newstable[7][6] = 6;
146 newstable[7][7] = 2;
147 newstable[8][0] = 4;
148 newstable[8][1] = 5;
149 newstable[8][2] = 9;
150 newstable[8][3] = 13;
151 newstable[8][4] = 12;
152 newstable[8][5] = 15;
153 newstable[8][6] = 11;
154 newstable[8][7] = 7;
155 newstable[9][0] = 5;
156 newstable[9][1] = 6;
157 newstable[9][2] = 10;
158 newstable[9][3] = 14;
159 newstable[9][4] = 13;
160 newstable[9][5] = 12;
161 newstable[9][6] = 8;
162 newstable[9][7] = 4;
163 newstable[10][0] = 6;
164 newstable[10][1] = 7;
165 newstable[10][2] = 11;
166 newstable[10][3] = 15;
167 newstable[10][4] = 14;
168 newstable[10][5] = 13;
169 newstable[10][6] = 9;
170 newstable[10][7] = 5;
171 newstable[11][0] = 7;
172 newstable[11][1] = 4;
173 newstable[11][2] = 8;
174 newstable[11][3] = 12;
175 newstable[11][4] = 15;
176 newstable[11][5] = 14;
177 newstable[11][6] = 10;
178 newstable[11][7] = 6;
179 newstable[12][0] = 8;
180 newstable[12][1] = 9;
181 newstable[12][2] = 13;
182 newstable[12][3] = 1;
183 newstable[12][4] = 0;
184 newstable[12][5] = 3;
185 newstable[12][6] = 15;
186 newstable[12][7] = 11;
187 newstable[13][0] = 9;
188 newstable[13][1] = 10;
189 newstable[13][2] = 14;
190 newstable[13][3] = 2;
191 newstable[13][4] = 1;
192 newstable[13][5] = 0;
193 newstable[13][6] = 12;
194 newstable[13][7] = 8;
195 newstable[14][0] = 10;
196 newstable[14][1] = 11;
197 newstable[14][2] = 15;
198 newstable[14][3] = 3;
199 newstable[14][4] = 2;
200 newstable[14][5] = 1;
201 newstable[14][6] = 13;
202 newstable[14][7] = 9;
203 newstable[15][0] = 11;
204 newstable[15][1] = 8;
205 newstable[15][2] = 12;
206 newstable[15][3] = 0;
207 newstable[15][4] = 3;
208 newstable[15][5] = 2;
209 newstable[15][6] = 14;
210 newstable[15][7] = 10;
211 end // initial begin
212
213 reg [3:0] flags_addr_latch;
214 reg [3:0] flags_addr;
215
216 always @* begin
217 if(flags_addr_latch)
218 flags_addr <= flags_addr_latch;
219 else
220 case(op)
221 `OP_LOADA:
222 flags_addr <= flagr;
223 `OP_LOADB:
224 flags_addr <= cond;
225 `OP_STORE:
226 flags_addr <= flagw;
227 default:
228 flags_addr <= 0;
229 endcase
230 end // always @ *
231
232 reg [15:0] flags_in;
233 wire [15:0] flags_out;
234 reg flags_write;
235
236 reg [15:0] latest_news;
237
238 RAM #(.ADDRESS_BITS(3)) flags (.clk(clk), .write(flags_write), .addr(flags_addr[2:0]), .in(flags_in), .out(flags_out));
239
240 reg [15:0] flag_or_news;
241
242 reg [15:0] newsidx;
243
244 always @* begin
245 if(flags_addr[3]) begin // read from news
246 for(idx = 0; idx < 16; idx++) begin
247 newsidx = newstable[idx][flags_addr[2:0]];
248 flag_or_news[idx] = latest_news[newsidx];
249 end
250 end else begin
251 flag_or_news = flags_out;
252 end
253 end
254
255 always @ (posedge clk) begin
256 if(mem_write)
257 mem_write <= 0;
258 if(flags_write) begin
259 flags_write <= 0;
260 flags_addr_latch <= 0;
261 end
262
263 case (op)
264 `OP_NOP: begin end
265
266 `OP_LOADA:
267 begin
268 alu_carry <= aluc;
269 F <= flag_or_news;
270 A <= mem_out;
271 C <= mem_out;
272 io <= io_pin;
273 if (bsel)
274 B <= cube_in;
275 end
276
277 `OP_LOADB:
278 begin
279 alu_sum <= alus;
280 Cond <= inv ? ~flag_or_news : flag_or_news;
281 B <= mem_out;
282 R <= mem_out;
283 end
284
285 `OP_STORE:
286 begin
287 for(idx = 0; idx < 16; idx++) begin
288 flags_in[idx] = Cond[idx] ? alu_carry_out[idx] : flags_out[idx];
289 latest_news[idx] <= flags_in[idx];
290 end
291 if(flags_addr) begin // we do not write to flag 0
292 flags_write <= 1;
293 flags_addr_latch <= flags_addr;
294 end
295 mem_in <= alu_sum_out;
296 mem_write <= 1;
297 end
298
299 `OP_READ:
300 begin
301 if (CS)
302 mem_in <= mem_out;
303 end
304
305 `OP_LOADI:
306 begin
307 C <= mem_out;
308 A <= I;
309 alu_sum <= 8'b11110000; // out of A, B, F, select exactly A
310 end
311
312/* `OP_RUG:
313 begin
314 if(!rw && ac && !news)
315 begin
316 rug[reg_] <= A;
317 C <= mem_out;
318 end
319 if(!rw && !ac && !news)
320 begin
321 rug[reg_] <= C;
322 A <= mem_out;
323 end
324 if(rw && ac && !news)
325 begin
326 A <= rug[reg_];
327 mem_in <= C;
328 end
329 if(rw && !ac && !news)
330 begin
331 C <= rug[reg_];
332 mem_in <= A;
333 end
334 if(rw && !ac && news)
335 begin
336 R <= mem_out;
337 cube_in <= mem_out;
338 end
339 if(rw && ac && news)
340 begin
341 cube_in <= mem_out;
342 end
343 end
344*/
345 endcase
346 end
347endmodule
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