]> iEval git - clump.git/blame_incremental - pll.v
Discover the PLL and multiply the CLK by 4
[clump.git] / pll.v
... / ...
CommitLineData
1/**
2 * PLL configuration
3 *
4 * This Verilog module was generated automatically
5 * using the icepll tool from the IceStorm project.
6 * Use at your own risk.
7 *
8 * Given input frequency: 12.000 MHz
9 * Requested output frequency: 48.000 MHz
10 * Achieved output frequency: 48.000 MHz
11 */
12
13module pll(
14 input clock_in,
15 output clock_out,
16 output locked
17 );
18
19SB_PLL40_CORE #(
20 .FEEDBACK_PATH("SIMPLE"),
21 .DIVR(4'b0000), // DIVR = 0
22 .DIVF(7'b0111111), // DIVF = 63
23 .DIVQ(3'b100), // DIVQ = 4
24 .FILTER_RANGE(3'b001) // FILTER_RANGE = 1
25 ) uut (
26 .LOCK(locked),
27 .RESETB(1'b1),
28 .BYPASS(1'b0),
29 .REFERENCECLK(clock_in),
30 .PLLOUTCORE(clock_out)
31 );
32
33endmodule
This page took 0.021417 seconds and 4 git commands to generate.