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[clump.git] / Makefile
1 DEVICE = hx1k
2
3 all: toplevel.bin
4
5 toplevel.bin: master.rpt master.bin worker.rpt worker.bin
6 tools/icestorm/icemulti/icemulti -o toplevel.bin -v -p0 worker.bin master.bin
7
8 master.blif: master.v
9 tools/yosys/yosys -p 'synth_ice40 -top master -blif $@' $<
10
11 worker.blif: worker.v
12 tools/yosys/yosys -p 'synth_ice40 -top worker -blif $@' $<
13
14 %.asc: %.pcf %.blif
15 tools/arachne-pnr/bin/arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^ -P tq144
16
17 %.bin: %.asc
18 tools/icestorm/icepack/icepack $< $@
19
20 %.rpt: %.asc
21 tools/icestorm/icetime/icetime -C tools/icestorm/icebox/chipdb-$(subst hx,,$(subst lp,,$(DEVICE))).txt -d $(DEVICE) -mtr $@ $<
22
23 prog: toplevel.bin
24 tools/icestorm/iceprog/iceprog $<
25
26 progall: toplevel.bin
27 bash progall.sh
28
29 progmaster: master.bin
30 tools/icestorm/iceprog/iceprog $<
31
32 clean:
33 rm -f master.blif master.asc worker.blif worker.asc master.bin worker.bin toplevel.bin
34
35
36 sim:
37 tools/yosys/yosys -p 'read_verilog -sv -DSIM worker.v; prep -top worker -nordff; sim -clock CLKin -vcd test.vcd -n 3000'
38
39 .PHONY: all prog clean sim
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