]> iEval git - clump.git/blob - Makefile
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[clump.git] / Makefile
1 PROJ = master
2 PIN_DEF = master.pcf
3 DEVICE = hx1k
4
5 all: $(PROJ).rpt $(PROJ).bin
6
7 %.blif: %.v
8 tools/yosys/yosys -p 'synth_ice40 -top master -blif $@' $<
9
10 %.asc: $(PIN_DEF) %.blif
11 tools/arachne-pnr/bin/arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^ -P tq144
12
13 %.bin: %.asc
14 tools/icestorm/icepack/icepack $< $@
15
16 %.rpt: %.asc
17 tools/icestorm/icetime/icetime -C tools/icestorm/icebox/chipdb-$(subst hx,,$(subst lp,,$(DEVICE))).txt -d $(DEVICE) -mtr $@ $<
18
19 prog: $(PROJ).bin
20 tools/icestorm/iceprog/iceprog $<
21
22 clean:
23 rm -f $(PROJ).blif $(PROJ).asc $(PROJ).bin
24
25
26 sim:
27 tools/yosys/yosys -p 'read_verilog -sv -DSIM master.v; prep -top master -nordff; sim -clock CLKin -vcd test.vcd -n 3000'
28
29 .PHONY: all prog clean sim
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