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iEval git - clump.git/blob - Makefile
e2c55e51e8aeba470fb0bc42aa38029f57958b53
5 all: $(PROJ
).rpt
$(PROJ
).bin
8 tools
/yosys
/yosys
-p
'synth_ice40 -top master -blif $@' $<
10 %.asc
: $(PIN_DEF
) %.blif
11 tools
/arachne-pnr
/bin
/arachne-pnr
-d
$(subst hx
,,$(subst lp
,,$(DEVICE
))) -o
$@
-p
$^
-P tq144
14 tools
/icestorm
/icepack
/icepack
$< $@
17 tools
/icestorm
/icetime
/icetime
-C tools
/icestorm
/icebox
/chipdb-
$(subst hx
,,$(subst lp
,,$(DEVICE
))).txt
-d
$(DEVICE
) -mtr
$@
$<
20 tools
/icestorm
/iceprog
/iceprog
$<
23 rm -f
$(PROJ
).blif
$(PROJ
).asc
$(PROJ
).bin
27 tools
/yosys
/yosys
-p
'read_verilog -sv -DSIM master.v; prep -top master -nordff; sim -clock CLKin -vcd test.vcd -n 3000'
29 .PHONY
: all prog
clean sim
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