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1 `include "ram.v"
2 `include "chip.v"
3 `include "uart.v"
4
5 module toplevel (input CLKin, output [4:0] led, output uart_tx, input uart_rx);
6 wire clk = CLKin;
7
8 wire [11:0] mem_addr;
9 wire [15:0] mem_in;
10 wire [15:0] mem_out;
11 wire mem_write;
12
13 RAM #(.ADDRESS_BITS(12)) ram (.clk(clk), .write(mem_write), .addr(mem_addr), .in(mem_in), .out(mem_out));
14
15 reg [7:0] from_uart [3:0];
16 reg [2:0] uart_ptr = 0;
17
18 wire [15:0] I = {from_uart[1], from_uart[0]};
19 assign mem_addr = from_uart[2];
20 wire [2:0] op_from_uart = from_uart[3][2:0];
21 wire CS = from_uart[3][3];
22
23 reg [2:0] op = 0;
24
25 assign led = uart_ptr;
26
27 chip chip (.clk(clk), .op(op), .I(I), .io_pin(0), .CS(CS), .mem_in(mem_in), .mem_out(mem_out), .mem_write(mem_write));
28
29 wire received;
30 wire [7:0] rx_byte;
31 reg transmit = 0;
32 reg [7:0] tx_byte;
33
34 uart uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .received(received), .transmit(transmit), .tx_byte(tx_byte), .rx_byte(rx_byte));
35
36 reg [15:0] rom_I [0:5];
37 reg [7:0] rom_mem_addr [0:5];
38 reg [2:0] rom_op [0:5];
39 reg rom_CS [0:5];
40
41 reg [2:0] state = 0;
42
43 always @ (posedge clk) begin
44 if (received) begin
45 from_uart[uart_ptr] <= rx_byte;
46 uart_ptr <= uart_ptr + 1;
47 end
48
49 if (uart_ptr == 4) begin
50 op <= op_from_uart;
51 uart_ptr <= 0;
52 state <= 1;
53 end
54
55 if (state == 1) begin
56 transmit <= 1;
57 tx_byte <= mem_in;
58 state <= 2;
59 end
60
61 if (state == 2) begin
62 transmit <= 0;
63 state <= 0;
64 end
65
66 if (op != 0) begin
67 op <= 0;
68 end
69 end
70 endmodule
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