5 module toplevel (input CLKin, output [4:0] led, output uart_tx, input uart_rx);
13 RAM #(.ADDRESS_BITS(12)) ram (.clk(clk), .write(mem_write), .addr(mem_addr), .in(mem_in), .out(mem_out));
15 reg [7:0] from_uart [3:0];
16 reg [2:0] uart_ptr = 0;
18 wire [15:0] I = {from_uart[1], from_uart[0]};
19 assign mem_addr = from_uart[2];
20 wire [2:0] op_from_uart = from_uart[3][2:0];
21 wire CS = from_uart[3][3];
25 assign led = uart_ptr;
27 chip chip (.clk(clk), .op(op), .I(I), .io_pin(0), .CS(CS), .mem_in(mem_in), .mem_out(mem_out), .mem_write(mem_write));
34 uart uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .received(received), .transmit(transmit), .tx_byte(tx_byte), .rx_byte(rx_byte));
36 reg [15:0] rom_I [0:5];
37 reg [7:0] rom_mem_addr [0:5];
38 reg [2:0] rom_op [0:5];
43 always @ (posedge clk) begin
45 from_uart[uart_ptr] <= rx_byte;
46 uart_ptr <= uart_ptr + 1;
49 if (uart_ptr == 4) begin