]> iEval git - clump.git/blob - yosys-sim-script
f82bfb456f6efde9e1f09e2f3d34d45b4e070ef6
[clump.git] / yosys-sim-script
1 read_verilog -sv -DSIM toplevel.v
2 prep -top cpu -nordff
3 sim -clock clk -vcd test.vcd -n 3000
This page took 0.035598 seconds and 4 git commands to generate.