Reset pins + add reader and writer

[yule.git] / reader.v

diff --git a/reader.v b/reader.v
new file mode 100644 (file)
index 0000000..8386b53
--- /dev/null
+++ b/reader.v
@@ -0,0 +1,55 @@
+`define STATE_IDLE    2'd0
+`define STATE_LENGTH  2'd1
+`define STATE_READ1   2'd2
+`define STATE_READ2   2'd3
+
+module READER (input clk, input clk_enable, input [7:0] uart_rx_byte, input uart_rx_signal, input uart_is_receiving, output reg active, output reg ram_we, output [12:0] ram_addr, output reg [15:0] ram_di);
+   reg [1:0] state = `STATE_IDLE;
+
+   reg [12:0] bytes_left = 0;
+   reg [12:0] current_index = 0;
+
+   assign ram_addr = current_index;
+
+   always @ (posedge clk)
+        if (clk_enable) begin
+               if(!uart_rx_signal) ram_we <= 0;
+
+               case(state)
+                 `STATE_IDLE: begin
+                        if(uart_rx_signal) begin
+                               bytes_left[12:8] <= uart_rx_byte[4:0];
+                               bytes_left[7:0] <= 0;
+                               current_index <= -1;
+                               active <= 1;
+                               state <= `STATE_LENGTH;
+                        end else
+                          active <= 0;
+                 end
+
+                 `STATE_LENGTH: begin
+                        if(uart_rx_signal) begin
+                               bytes_left[7:0] <= uart_rx_byte;
+                               state <= `STATE_READ1;
+                        end
+                 end
+
+                 `STATE_READ1: begin
+                        if(uart_rx_signal) begin
+                               ram_di[15:8] <= uart_rx_byte;
+                               current_index <= current_index + 1;
+                               bytes_left <= bytes_left - 1;
+                               state <= `STATE_READ2;
+                        end
+                 end
+
+                 `STATE_READ2: begin
+                        if(uart_rx_signal) begin
+                               ram_di[7:0] <= uart_rx_byte;
+                               ram_we <= 1;
+                               state <= |bytes_left ? `STATE_READ1 : `STATE_IDLE;
+                        end
+                 end
+               endcase
+        end
+endmodule