worker/master split

[clump.git] / worker.v

diff --git a/worker.v b/worker.v
new file mode 100644 (file)
index 0000000..7a5a909
--- /dev/null
+++ b/worker.v
@@ -0,0 +1,160 @@
+`include "pll.v"
+`include "ram.v"
+`include "chip.v"
+`include "uart.v"
+
+`ifdef SIM
+ `define UART_DIVIDE 1
+`else
+ `define UART_DIVIDE 1
+ // s/192/3/ for 19200 baud uart
+`endif
+
+module worker (input CLKin, output [4:0] led, output uart_tx, input uart_rx, output reg ready_out = 1, input ready_in);
+   wire clk;
+   wire clk_tmp;
+
+   //pll pll (.clock_in(CLKin), .clock_out(clk));
+
+   reg [20:0] counter = 0;
+
+   reg                   clk = 0;
+
+   always @ (posedge CLKin) begin
+         if(counter == 5000) begin
+                counter <= 0;
+                clk <= 1 - clk;
+         end
+         else
+               counter <= counter + 1;
+   end
+
+   wire [11:0] mem_addr;
+   wire [63:0] mem_in;
+   wire [63:0] mem_out;
+   wire           mem_write;
+
+   RAM #(.ADDRESS_BITS(8)) ram (.clk(clk), .write(mem_write), .addr(mem_addr), .in(mem_in), .out(mem_out));
+
+   reg [7:0]   from_uart [3:0];
+   reg [2:0]   uart_ptr = 0;
+
+   wire [15:0] I  = {from_uart[1], from_uart[0]};
+   assign mem_addr = from_uart[2];
+   wire [2:0]  op_from_uart = from_uart[3][2:0];
+   wire           CS = from_uart[3][3];
+
+   reg [2:0]   op = 0;
+
+   reg [2:0]   last_op = 0;
+
+   reg [15:0]  I;
+   reg                    CS;
+
+   chip chip (.clk(clk), .op(op), .I(I), .io_pin(0), .CS(CS), .mem_in(mem_in), .mem_out(mem_out), .mem_write(mem_write));
+
+   wire           received;
+   wire [7:0]  rx_byte;
+   reg                    transmit = 0;
+   reg  [7:0]  tx_byte = 0;
+   wire           is_receiving;
+   wire           is_transmitting;
+
+   // 19200 (actually 300) baud uart
+   uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .received(received), .transmit(transmit), .tx_byte(tx_byte), .rx_byte(rx_byte), .is_receiving(is_receiving), .is_transmitting(is_transmitting));
+
+   assign led[0] = is_transmitting;
+   assign led[4] = received;
+//   assign led[3:1] = last_op;
+
+   assign led[2] = |mem_out; // so that mem_out is used
+
+   // 0 is idle
+`define STATE_IDLE 0
+`define STATE_PROPAGATE 1
+`define STATE_EXECUTE 2
+`define STATE_ROUTE 3
+
+   reg [5:0]   state = 0;
+
+//   assign led[4:2] = state;
+
+   always @ (posedge clk) begin
+         case(state)
+               `STATE_IDLE: begin
+                  if(uart_ptr == 4) begin
+                         last_op <= op_from_uart;
+                         uart_ptr <= 0;
+                         state <= `STATE_PROPAGATE;
+                         ready_out <= 0;
+                  end
+                  else if (received) begin
+                         from_uart[uart_ptr] <= rx_byte;
+                         uart_ptr <= uart_ptr + 1;
+                  end else
+                        ready_out <= 1;
+               end
+
+               `STATE_PROPAGATE: begin
+                  if(transmit)
+                         transmit <= 0;
+                  else if(uart_ptr == 4) begin
+                         uart_ptr <= 0;
+                         if(op == `OP_ROUTE) begin
+                                state <= `STATE_ROUTE;
+                         end else begin
+                                op <= last_op;
+                                state <= `STATE_EXECUTE;
+                         end
+                  end else if(!is_transmitting && ready_in) begin
+                         tx_byte <= from_uart[uart_ptr];
+                         transmit <= 1;
+                         uart_ptr <= uart_ptr + 1;
+                  end
+               end
+
+               `STATE_EXECUTE: begin
+                  op <= 0;
+                  state <= `STATE_IDLE;
+               end
+
+               `STATE_ROUTE: begin
+                  state <= `STATE_IDLE; // for now
+               end
+         endcase
+
+         /*
+
+         if (state == 1 && op != `OP_READ) begin
+                op <= 0;
+                state <= 0;
+         end
+
+         if (state == 1 && op == `OP_READ) begin
+                op <= 0;
+                state <= 2;
+                transmit <= 1;
+                tx_byte <= mem_out[7:0];
+         end
+
+         if (state == 2 && transmit) begin
+                transmit <= 0;
+         end
+
+         if (state == 2 && !transmit && !is_transmitting) begin
+                state <= 3;
+                transmit <= 1;
+                tx_byte <= mem_out[15:8];
+         end
+
+         if (state == 3) begin
+                transmit <= 0;
+                state <= 0;
+         end */
+   end
+
+   wire ready = (state == 0 && !is_receiving);
+
+   assign ready_out = ready_in & ready;
+
+endmodule