X-Git-Url: http://git.ieval.ro/?a=blobdiff_plain;f=Makefile;fp=Makefile;h=0fb0a575be3498fa5c8ebb7dc58637598ad34449;hb=23c26e0422eda4cb868569e6c3cc4f41fe6e2864;hp=64606370a5316b756a95158e6f162cf6fe53d260;hpb=5a2a82dc19c5d46c250c101202a43ee8375c2e28;p=clump.git

diff --git a/Makefile b/Makefile
index 6460637..0fb0a57 100644
--- a/Makefile
+++ b/Makefile
@@ -22,4 +22,8 @@ prog: $(PROJ).bin
 clean:
 	rm -f $(PROJ).blif $(PROJ).asc $(PROJ).bin
 
-.PHONY: all prog clean
+
+sim:
+	tools/yosys/yosys -p 'read_verilog -sv -DSIM toplevel.v; prep -top toplevel -nordff; sim -clock CLKin -vcd test.vcd -n 3000'
+
+.PHONY: all prog clean sim