X-Git-Url: http://git.ieval.ro/?a=blobdiff_plain;f=asm.pm;fp=asm.pm;h=269b8d1d49d62963131325ce32f42e95e1e0f3ca;hb=7f1b6bd9e0070ddc074215defc46d64abef645ac;hp=492bfccc1e2764dce4e1a4c0f20a3f615a17e854;hpb=3b542afc856d736dfd2ff0eed081f647de07af4c;p=clump.git

diff --git a/asm.pm b/asm.pm
index 492bfcc..269b8d1 100644
--- a/asm.pm
+++ b/asm.pm
@@ -7,10 +7,10 @@ use constant +{
 	OP_LOADA => 1,
 	OP_LOADB => 2,
 	OP_STORE => 3,
-	OP_READ => 4,
+	OP_STOREI => 4,
 	OP_LOADI => 5,
 	OP_ROUTE => 6,
-	OP_RUG => 7,
+	OP_LED => 7,
 };
 
 q,
@@ -28,19 +28,22 @@ $port->read_const_time(2000);
 $port->write_settings or die "$!";
 ,;
 
-use Fcntl;
+#use Fcntl;
 use Time::HiRes qw/sleep/;
 
-sysopen my $port, '/dev/ttyUSB1', O_SYNC | O_RDWR or die "$!";
+my $port;
+#sysopen $port, '/dev/ttyUSB1', O_SYNC | O_RDWR or die "$!";
 
 
 use parent qw/Exporter/;
-our @EXPORT = qw/loada loadb store write_verilog alu_select_a alu_select_b alu_select_f alu_zero flag_zero flag_news alu_xor alu_xnor alu_or alu_of_function aluc_add alus_add aluc_addAF alus_addAF alu2 alu3 add addC/;
-our @EXPORT_OK = qw/loada loadb store write_verilog alu_select_a alu_select_b alu_select_f alu_zero flag_zero flag_news  alu_xor alu_xnor alu_or alu_of_function aluc_add alus_add aluc_addAF alus_addAF alu2 alu3 add addC/;
+our @EXPORT = qw/loada loadb store write_verilog alu_select_a alu_select_b alu_select_f alu_zero flag_zero flag_news alu_xor alu_xnor alu_or alu_of_function aluc_add alus_add aluc_addAF alus_addAF alu2 alu3 add addC loadi storei ledm ledi route/;
+our @EXPORT_OK = qw/loada loadb store write_verilog alu_select_a alu_select_b alu_select_f alu_zero flag_zero flag_news  alu_xor alu_xnor alu_or alu_of_function aluc_add alus_add aluc_addAF alus_addAF alu2 alu3 add addC loadi storei ledm ledi route/;
 
 use File::Slurp::Tiny 'write_file';
 
-sub send_ {
+=begin comment
+
+sub send__ {
 	my ($cmd) = @_;
 	my %cmd = %$cmd;
 
@@ -60,6 +63,29 @@ sub send_ {
 	}
 }
 
+=end
+
+
+=cut
+
+my $rom_cnt = 0;
+
+sub send_ {
+	my ($cmd) = @_;
+	my %cmd = %$cmd;
+
+	my $binary = pack 'vCC', @cmd{qw/I mem_addr op/}; # we ignore CS for now
+	my $hex = reverse unpack 'h*', $binary;
+	say "$rom_cnt: data <= 32'h$hex;";
+	$rom_cnt++;
+}
+
+
+sub nop {
+	send_
+	  { I => 0, mem_addr => 0, op => OP_NOP, CS => 0 }
+  }
+
 sub loada {
 	my ($addr, $flagr, $bsel, $aluc) = @_;
 	my $I = 0;
@@ -80,10 +106,10 @@ sub loadb {
 	  { I => $I, mem_addr => $addr, op => OP_LOADB, CS => 0 }
   }
 
-sub read_ {
-	my ($addr) = @_;
-	send_ { I => 0, mem_addr => $addr, op => OP_READ, CS => 1 }
-}
+#sub read_ {
+#	my ($addr) = @_;
+#	send_ { I => 0, mem_addr => $addr, op => OP_READ, CS => 1 }
+#}
 
 sub store {
 	my ($addr, $flagw, $edge_, $cube) = @_;
@@ -101,6 +127,37 @@ sub loadi {
 	  { I => $I, mem_addr => $addr, op => OP_LOADI, CS => 0 }
 }
 
+sub route {
+	my ($addr, $dest_addr) = @_;
+	my $I = $dest_addr;
+	send_
+	  { I => $I, mem_addr => $addr, op => OP_ROUTE, CS => 0 }
+}
+
+sub storei {
+	my ($addr, $I) = @_;
+	send_
+	  { I => $I, mem_addr => $addr, op => OP_STOREI, CS => 0 }
+}
+
+sub led {
+	my ($addr, $mode, $offset_leds) = @_;
+	my $I = $offset_leds;
+	$I |= $mode << 4;
+	send_
+	  { I => $I, mem_addr => $addr, op => OP_LED, CS => 0 }
+}
+
+sub ledm {
+	my ($addr, $offset) = @_;
+	led $addr, 1, $offset;
+}
+
+sub ledi {
+	my ($leds) = @_;
+	led 0, 0, $leds;
+}
+
 sub flag_zero { 0 }
 sub flag_temp { 7 }
 
@@ -227,3 +284,5 @@ sub news_ff {
 	alu3 alu_select_f, alu_select_a, 0, 0, 0, $flagIN, flag_zero;
 	news_generic $nX, $nY, {flag => $flagOUT};
 }
+
+1;