X-Git-Url: http://git.ieval.ro/?a=blobdiff_plain;f=lisp_processor.v;fp=lisp_processor.v;h=a3b1966d8bc7949336560eef04c53a7c639535eb;hb=08f239778273f85e61256a718d8970e4e1fa4592;hp=b22f3f1fd4dd6d0d5400566ee012f2685fe33507;hpb=62e5ccb8304550f88f658af70a683936d47c08b2;p=yule.git

diff --git a/lisp_processor.v b/lisp_processor.v
index b22f3f1..a3b1966 100644
--- a/lisp_processor.v
+++ b/lisp_processor.v
@@ -3,6 +3,7 @@
 `include "reader.v"
 `include "uart.v"
 `include "writer.v"
+`include "controller.v"
 
 `define GCOP_NOP      4'd0
 `define GCOP_CDR      4'd1
@@ -21,16 +22,6 @@
 `define GCOP_RDQA     4'd14
 `define GCOP_RDQCDRRX 4'd15
 
-`define STATE_READ  3'b100
-`define STATE_RUN   3'b010
-`define STATE_WRITE 3'b001
-
-`ifdef SIM
- `define START_STATE `STATE_RUN
-`else
- `define START_STATE `STATE_READ
-`endif
-
 `ifdef SIM
  `define UART_DIVIDE 1
 `else
@@ -38,23 +29,6 @@
 `endif
 
 module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx);
-   reg [3:0] state = `START_STATE;
-
-   wire 	 is_reading = state == `STATE_READ;
-   wire 	 is_running = state == `STATE_RUN;
-   wire 	 is_writing = state == `STATE_WRITE;
-
-   wire reset = !is_running;
-   reg 	counter = 0;
-
-   wire gc_clock_enable   = is_running;
-   wire eval_clock_enable = step_eval & is_running;
-   wire reader_clock_enable = is_reading;
-   wire writer_clock_enable = is_writing;
-
-   always @ (posedge clk)
-	 counter <= counter + 1;
-
    wire [12:0] P;
    wire [15:0] E1;
    wire [15:0] E2;
@@ -76,19 +50,28 @@ module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx);
 
    wire [12:0] writer_ram_addr;
 
-   wire        ram_we = reader_clock_enable ? reader_ram_we : gc_ram_we;
-   wire [12:0] ram_addr = reader_clock_enable ? reader_ram_addr : writer_clock_enable ? writer_ram_addr : gc_ram_addr;
-   wire [15:0] ram_di = reader_clock_enable ? reader_ram_di : gc_ram_di;
+   wire        ram_we;
+   wire [12:0] ram_addr;
+   wire [15:0] ram_di;
    wire [15:0] ram_do;
 
+   wire 	   eval_finished;
    wire 	   reader_finished;
    wire		   writer_finished;
 
+   wire 	   gc_clock_enable;
+   wire 	   eval_clock_enable;
+   wire 	   reader_clock_enable;
+   wire 	   writer_clock_enable;
+   wire 	   reset;
+
+   CTRL ctrl (.clk(clk), .step_eval(step_eval), .reader_finished(reader_finished), .eval_finished(eval_finished), .writer_finished(writer_finished), .gc_clock_enable(gc_clock_enable), .eval_clock_enable(eval_clock_enable), .reader_clock_enable(reader_clock_enable), .writer_clock_enable(writer_clock_enable), .reset(reset), .gc_ram_we(gc_ram_we), .reader_ram_we(reader_ram_we), .gc_ram_addr(gc_ram_addr), .reader_ram_addr(reader_ram_addr), .writer_ram_addr(writer_ram_addr), .gc_ram_di(gc_ram_di), .reader_ram_di(reader_ram_di), .ram_we(ram_we), .ram_addr(ram_addr), .ram_di(ram_di), .uart_is_receiving(uart_is_receiving), .uart_is_transmitting(uart_is_transmitting), .led(led));
+
    GCRAM gcram (.clk(clk), .we(ram_we), .addr(ram_addr), .di(ram_di), .do(ram_do));
 
    GC gc (.clk(clk), .rst(reset), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(gc_ram_we), .ram_addr(gc_ram_addr), .ram_di(gc_ram_di), .ram_do(ram_do), .Pout(P));
 
-   EVAL eval (.clk(clk), .rst(reset), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et));
+   EVAL eval (.clk(clk), .rst(reset), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et), .eval_finished(eval_finished));
 
    READER reader (.clk(clk), .clk_enable(reader_clock_enable), .rx_byte(uart_rx_byte), .rx_signal(uart_rx_signal), .finished(reader_finished), .ram_we(reader_ram_we), .ram_addr(reader_ram_addr), .ram_di(reader_ram_di));
 
@@ -105,24 +88,6 @@ module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx);
    wire 	  uart_tx_signal;
    wire [7:0] uart_tx_byte;
 
-   always @ (posedge clk) begin
-	  if(is_writing & writer_finished)
-		state <= `STATE_READ;
-
-	  if(is_reading & reader_finished)
-		state <= `STATE_RUN;
-
-	  if(is_running & eostate == 5'd7)
-		state <= `STATE_WRITE;
-   end
-
    // 4800 baud uart
    uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error));
-
-   // Assign the outputs
-   assign led[0] = is_reading;
-   assign led[1] = uart_is_receiving;
-   assign led[2] = is_writing;
-   assign led[3] = uart_is_transmitting;
-   assign led[4] = is_running;
 endmodule