X-Git-Url: http://git.ieval.ro/?a=blobdiff_plain;f=master.v;fp=master.v;h=b54abe9ad0e9ef94025b22001e66658e9082ff39;hb=7f1b6bd9e0070ddc074215defc46d64abef645ac;hp=00573888f3fef398e3c8372ac72ae8315d0fd7d2;hpb=3b542afc856d736dfd2ff0eed081f647de07af4c;p=clump.git

diff --git a/master.v b/master.v
index 0057388..b54abe9 100644
--- a/master.v
+++ b/master.v
@@ -26,8 +26,8 @@ module master(input CLKin, output [4:0] led, output uart_tx, input uart_rx, outp
 		counter <= counter + 1;
    end
 
-   reg [4:0] program_counter = 0;
-   wire [63:0] rom_output;
+   reg [3:0] program_counter = 0;
+   wire [31:0] rom_output;
 
    master_rom master_rom (.clk(clk), .addr(program_counter), .data(rom_output));
 
@@ -35,6 +35,8 @@ module master(input CLKin, output [4:0] led, output uart_tx, input uart_rx, outp
 `define STATE_SEND 0
 `define STATE_WAIT_PROPAGATE 1
 `define STATE_WAIT_NEWS 2
+`define STATE_PROPAGATE_NEWS 3
+`define STATE_WASTE_TIME 4
 
    reg [5:0] state = `STATE_SEND;
    reg [5:0] uart_ptr = 0;
@@ -49,6 +51,13 @@ module master(input CLKin, output [4:0] led, output uart_tx, input uart_rx, outp
    // 19200 (actually 300) baud uart
    uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .received(received), .transmit(transmit), .tx_byte(tx_byte), .rx_byte(rx_byte), .is_receiving(is_receiving), .is_transmitting(is_transmitting));
 
+   reg [15:0]  waste_counter = 0;
+
+   reg [7:0]   saved_news [3:0];
+
+   assign led[4] = state != `STATE_WASTE_TIME;
+   assign led[3:0] = 0;
+
    always @(posedge clk) begin
 	  case(state)
 		`STATE_SEND: begin
@@ -57,7 +66,10 @@ module master(input CLKin, output [4:0] led, output uart_tx, input uart_rx, outp
 		   end else if(uart_ptr == 4) begin
 			  program_counter <= program_counter + 1;
 			  uart_ptr <= 0;
-			  state <= `STATE_WAIT_PROPAGATE;
+			  if(rom_output[26:24] == 6) // `OP_ROUTE
+				state <= `STATE_WAIT_NEWS;
+			  else
+				state <= `STATE_WAIT_PROPAGATE;
 		   end else if(!is_transmitting && ready_in) begin
 			  tx_byte <= rom_output[uart_ptr * 8 +: 8];
 			  transmit <= 1;
@@ -67,12 +79,44 @@ module master(input CLKin, output [4:0] led, output uart_tx, input uart_rx, outp
 
 		`STATE_WAIT_PROPAGATE: begin
 		   if(received) begin
-			  state <= `STATE_SEND;
+			  state <= `STATE_WASTE_TIME;
 		   end
 		end
 
+		`STATE_WASTE_TIME: begin
+		   if(waste_counter == 100) begin
+			  waste_counter <= 0;
+			  state <= `STATE_SEND;
+		   end else
+			 waste_counter <= waste_counter + 1;
+		end
+
 		`STATE_WAIT_NEWS: begin
+		   /** On a route instruction, we:
+			   - receive the instruction back
+			   - receive the news
+			   - propagate the news
+			   - go back to `STATE_SEND
+			*/
+		   if(uart_ptr == 8) begin
+			  state <= `STATE_PROPAGATE_NEWS;
+			  uart_ptr <= 0;
+		   end else if(received) begin
+			  if(uart_ptr[2]) /* uart_ptr >= 4 */
+				saved_news[uart_ptr[1:0]] <= rx_byte;
+			  uart_ptr <= uart_ptr + 1;
+		   end
+		end // case: `STATE_WAIT_NEWS
 
+		`STATE_PROPAGATE_NEWS: begin
+		   if(uart_ptr == 4) begin
+			  state <= `STATE_WASTE_TIME;
+			  uart_ptr <= 0;
+		   end else if(!is_transmitting && ready_in) begin
+			  tx_byte <= saved_news[uart_ptr];
+			  transmit <= 1;
+			  uart_ptr <= uart_ptr + 1;
+		   end
 		end
 	  endcase
    end