X-Git-Url: http://git.ieval.ro/?a=blobdiff_plain;f=pll.v;fp=pll.v;h=38745add1b4aa8322ca7096f7948c792dc6fcf56;hb=3e7694a3bd6a2d6e2d19a266f807078ab92ad1b7;hp=0000000000000000000000000000000000000000;hpb=2fb3df000de59bec2436a88db662c9ab94d69f33;p=yule.git

diff --git a/pll.v b/pll.v
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--- /dev/null
+++ b/pll.v
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+/**
+ * PLL configuration
+ *
+ * This Verilog module was generated automatically
+ * using the icepll tool from the IceStorm project.
+ * Use at your own risk.
+ *
+ * Given input frequency:        12.000 MHz
+ * Requested output frequency:   48.000 MHz
+ * Achieved output frequency:    48.000 MHz
+ */
+
+module pll(
+	input  clock_in,
+	output clock_out,
+	output locked
+	);
+
+SB_PLL40_CORE #(
+		.FEEDBACK_PATH("SIMPLE"),
+		.DIVR(4'b0000),		// DIVR =  0
+		.DIVF(7'b0111111),	// DIVF = 63
+		.DIVQ(3'b100),		// DIVQ =  4
+		.FILTER_RANGE(3'b001)	// FILTER_RANGE = 1
+	) uut (
+		.LOCK(locked),
+		.RESETB(1'b1),
+		.BYPASS(1'b0),
+		.REFERENCECLK(clock_in),
+		.PLLOUTCORE(clock_out)
+		);
+
+endmodule