From: Marius Gavrilescu Date: Thu, 1 Mar 2018 14:39:42 +0000 (+0000) Subject: Writer now works fine X-Git-Url: http://git.ieval.ro/?a=commitdiff_plain;h=2155cfe39d5e2b85a06e0df92658e30aade8fc0e;p=clump.git Writer now works fine --- diff --git a/lisp_processor.v b/lisp_processor.v index 2ffb4ca..910b173 100644 --- a/lisp_processor.v +++ b/lisp_processor.v @@ -122,5 +122,6 @@ module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx); assign led[0] = eval_clock_enable; assign led[1] = uart_is_transmitting; assign led[2] = uart_is_receiving; + assign led[3] = writer_finished; assign led[4] = !reset; endmodule diff --git a/writer.v b/writer.v index 37f6e0a..c68a8af 100644 --- a/writer.v +++ b/writer.v @@ -11,7 +11,7 @@ module WRITER (input clk, input clk_enable, output reg [7:0] uart_tx_byte, outpu assign ram_addr = current_index; - always @ (posedge clk) + always @ (posedge clk) begin if (clk_enable) begin if(uart_tx_signal) uart_tx_signal <= 0; @@ -50,5 +50,8 @@ module WRITER (input clk, input clk_enable, output reg [7:0] uart_tx_byte, outpu end end endcase // case (state) - end + end // if (clk_enable) + else + finished <= 0; + end endmodule