From: Marius Gavrilescu Date: Thu, 22 Mar 2018 20:02:44 +0000 (+0200) Subject: Discover the PLL and multiply the CLK by 4 X-Git-Url: http://git.ieval.ro/?a=commitdiff_plain;h=3e7694a3bd6a2d6e2d19a266f807078ab92ad1b7;p=clump.git Discover the PLL and multiply the CLK by 4 --- diff --git a/lisp_processor.pcf b/lisp_processor.pcf index 92d1b64..9c20287 100644 --- a/lisp_processor.pcf +++ b/lisp_processor.pcf @@ -17,4 +17,4 @@ set_io uart_tx 8 set_io uart_rx 9 # 12 MHz clock -set_io clk 21 +set_io CLKin 21 diff --git a/lisp_processor.v b/lisp_processor.v index f856aa2..fbc4467 100644 --- a/lisp_processor.v +++ b/lisp_processor.v @@ -1,3 +1,4 @@ +`include "pll.v" `include "gc.v" `include "eval.v" `include "reader.v" @@ -28,7 +29,11 @@ `define UART_DIVIDE 625 `endif -module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx); +module cpu (input CLKin, output [4:0] led, output uart_tx, input uart_rx); + wire clk; + + pll pll (.clock_in(CLKin), .clock_out(clk)); + wire [12:0] freeptr; wire [15:0] E1; wire [15:0] E2; @@ -88,6 +93,6 @@ module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx); wire uart_tx_signal; wire [7:0] uart_tx_byte; - // 4800 baud uart + // 19200 baud uart uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error)); endmodule diff --git a/pll.v b/pll.v new file mode 100644 index 0000000..38745ad --- /dev/null +++ b/pll.v @@ -0,0 +1,33 @@ +/** + * PLL configuration + * + * This Verilog module was generated automatically + * using the icepll tool from the IceStorm project. + * Use at your own risk. + * + * Given input frequency: 12.000 MHz + * Requested output frequency: 48.000 MHz + * Achieved output frequency: 48.000 MHz + */ + +module pll( + input clock_in, + output clock_out, + output locked + ); + +SB_PLL40_CORE #( + .FEEDBACK_PATH("SIMPLE"), + .DIVR(4'b0000), // DIVR = 0 + .DIVF(7'b0111111), // DIVF = 63 + .DIVQ(3'b100), // DIVQ = 4 + .FILTER_RANGE(3'b001) // FILTER_RANGE = 1 + ) uut ( + .LOCK(locked), + .RESETB(1'b1), + .BYPASS(1'b0), + .REFERENCECLK(clock_in), + .PLLOUTCORE(clock_out) + ); + +endmodule