From: Marius Gavrilescu Date: Mon, 19 Mar 2018 13:43:09 +0000 (+0200) Subject: Slightly simpler writer, P becomes freeptr X-Git-Url: http://git.ieval.ro/?a=commitdiff_plain;h=6414d51ab9e11e25d84a235e6f6f269c22143a9e;p=yule.git Slightly simpler writer, P becomes freeptr --- diff --git a/gc.v b/gc.v index 3020412..d05de63 100644 --- a/gc.v +++ b/gc.v @@ -1,6 +1,6 @@ `include "gcram.v" -module GC (input clk, input clk_enable, input rst, input [15:0] Ein, output [15:0] Eout, input [3:0] gcop, output [5:0] ostate, output conn_et, output conn_ea, output step_eval, output ram_we, output [12:0] ram_addr, output [15:0] ram_di, input [15:0] ram_do, output [12:0] Pout); +module GC (input clk, input clk_enable, input rst, input [15:0] Ein, output [15:0] Eout, input [3:0] gcop, output [5:0] ostate, output conn_et, output conn_ea, output step_eval, output ram_we, output [12:0] ram_addr, output [15:0] ram_di, input [15:0] ram_do, output [12:0] freeptr); reg [15:0] rom_output; reg [5:0] gostate; reg [5:0] gnstate; @@ -103,7 +103,7 @@ module GC (input clk, input clk_enable, input rst, input [15:0] Ein, output [15: reg [12:0] A; // latched address - assign Pout = P; + assign freeptr = P; assign ram_addr = A; assign ram_di = S; diff --git a/lisp_processor.v b/lisp_processor.v index a3b1966..f856aa2 100644 --- a/lisp_processor.v +++ b/lisp_processor.v @@ -29,7 +29,7 @@ `endif module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx); - wire [12:0] P; + wire [12:0] freeptr; wire [15:0] E1; wire [15:0] E2; wire [3:0] gcop; @@ -69,13 +69,13 @@ module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx); GCRAM gcram (.clk(clk), .we(ram_we), .addr(ram_addr), .di(ram_di), .do(ram_do)); - GC gc (.clk(clk), .rst(reset), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(gc_ram_we), .ram_addr(gc_ram_addr), .ram_di(gc_ram_di), .ram_do(ram_do), .Pout(P)); + GC gc (.clk(clk), .rst(reset), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(gc_ram_we), .ram_addr(gc_ram_addr), .ram_di(gc_ram_di), .ram_do(ram_do), .freeptr(freeptr)); EVAL eval (.clk(clk), .rst(reset), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et), .eval_finished(eval_finished)); READER reader (.clk(clk), .clk_enable(reader_clock_enable), .rx_byte(uart_rx_byte), .rx_signal(uart_rx_signal), .finished(reader_finished), .ram_we(reader_ram_we), .ram_addr(reader_ram_addr), .ram_di(reader_ram_di)); - WRITER writer (.clk(clk), .clk_enable(writer_clock_enable), .tx_byte(uart_tx_byte), .tx_signal(uart_tx_signal), .tx_busy(uart_is_transmitting), .finished(writer_finished), .ram_addr(writer_ram_addr), .ram_do(ram_do), .P(P)); + WRITER writer (.clk(clk), .clk_enable(writer_clock_enable), .tx_byte(uart_tx_byte), .tx_signal(uart_tx_signal), .tx_busy(uart_is_transmitting), .finished(writer_finished), .ram_addr(writer_ram_addr), .ram_do(ram_do), .freeptr(freeptr)); // UART outputs wire uart_rx_signal; diff --git a/writer.v b/writer.v index 1db21f1..c53d89f 100644 --- a/writer.v +++ b/writer.v @@ -3,11 +3,10 @@ `define STATE_WRITE2 2'b10 `define STATE_INCREMENT 2'b11 -module WRITER (input clk, input clk_enable, output reg [7:0] tx_byte, output reg tx_signal = 0, input tx_busy, output reg finished = 0, output [12:0] ram_addr, input [15:0] ram_do, input [12:0] P); +module WRITER (input clk, input clk_enable, output reg [7:0] tx_byte, output reg tx_signal = 0, input tx_busy, output reg finished = 0, output [12:0] ram_addr, input [15:0] ram_do, input [12:0] freeptr); reg [1:0] state = `STATE_START; reg [12:0] current_index; - reg [12:0] freeptr; assign ram_addr = current_index; @@ -18,9 +17,7 @@ module WRITER (input clk, input clk_enable, output reg [7:0] tx_byte, output reg case(state) `STATE_START: begin - finished <= 0; current_index <= 4; - freeptr <= P; state <= `STATE_WRITE1; end