From: Marius Gavrilescu Date: Wed, 6 Dec 2017 11:55:21 +0000 (+0200) Subject: Now works on iCEstick X-Git-Url: http://git.ieval.ro/?a=commitdiff_plain;h=9e30ab0cd6964785b3e01e2f3343e1fe4ee49462;p=clump.git Now works on iCEstick --- diff --git a/Makefile b/Makefile index f26533b..9c85adf 100644 --- a/Makefile +++ b/Makefile @@ -8,7 +8,7 @@ all: $(PROJ).rpt $(PROJ).bin yosys -p 'synth_ice40 -top top -blif $@' $< %.asc: $(PIN_DEF) %.blif - arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^ -P vq100 + arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^ -P tq144 %.bin: %.asc icepack $< $@ @@ -17,7 +17,7 @@ all: $(PROJ).rpt $(PROJ).bin icetime -d $(DEVICE) -mtr $@ $< prog: $(PROJ).bin - ./iCEburn.py -e -v -w $< + iceprog $< clean: rm -f $(PROJ).blif $(PROJ).asc $(PROJ).bin diff --git a/flash.pcf b/flash.pcf index 7426699..6ceab94 100644 --- a/flash.pcf +++ b/flash.pcf @@ -1,33 +1,67 @@ +# Generic iCEstick placement constraints file -set_io OUT_R[0] 72 -set_io OUT_R[1] 69 -set_io OUT_R[2] 66 - -set_io OUT_C[0] 87 -set_io OUT_C[1] 85 -set_io OUT_C[2] 82 -set_io OUT_C[3] 80 -set_io OUT_C[4] 78 -set_io OUT_C[5] 73 -set_io OUT_C[6] 71 -set_io OUT_C[7] 68 - -set_io IND[0] 86 -set_io IND[1] 83 -set_io IND[2] 81 -set_io IND[3] 79 - -set_io IN_R[0] 100 -set_io IN_R[1] 15 -set_io IN_R[2] 16 -set_io IN_R[3] 19 - -set_io IN_C[0] 90 -set_io IN_C[1] 93 -set_io IN_C[2] 95 -set_io IN_C[3] 97 - -set_io CLK 13 - -set_io UART_TX 10 -set_io UART_RX 9 \ No newline at end of file +# Red LEDs +set_io LED[0] 99 +set_io LED[1] 98 +set_io LED[2] 97 +set_io LED[3] 96 + +# Green LED +set_io LED[4] 95 + +# IrDA port +#set_io RXD 106 +#set_io TXD 105 +#set_io SD 107 + +# Pmod connector +#set_io PIO1_02 78 # Pin 1 +#set_io PIO1_03 79 # Pin 2 +#set_io PIO1_04 80 # Pin 3 +#set_io PIO1_05 81 # Pin 4 +#set_io PIO1_06 87 # Pin 7 +#set_io PIO1_07 88 # Pin 8 +#set_io PIO1_08 90 # Pin 9 +#set_io PIO1_09 91 # Pin 10 + +# Connector J1 +#set_io PIO0_02 112 # Pin 3 +#set_io PIO0_03 113 # Pin 4 +#set_io PIO0_04 114 # Pin 5 +#set_io PIO0_05 115 # Pin 6 +#set_io PIO0_06 116 # Pin 7 +#set_io PIO0_07 117 # Pin 8 +#set_io PIO0_08 118 # Pin 9 +#set_io PIO0_09 119 # Pin 10 + +# Connector J3 +#set_io PIO2_17 62 # Pin 3 +#set_io PIO2_16 61 # Pin 4 +#set_io PIO2_15 60 # Pin 5 +#set_io PIO2_14 56 # Pin 6 +#set_io PIO2_13 48 # Pin 7 +#set_io PIO2_12 47 # Pin 8 +#set_io PIO2_11 45 # Pin 9 +#set_io PIO2_10 44 # Pin 10 + +# FTDI Port B UART +#set_io DCDn 1 +#set_io DSRn 2 +#set_io DTRn 3 +#set_io CTSn 4 +#set_io RTSn 7 +set_io UART_TX 8 +set_io UART_RX 9 + +# SPI +#set_io SPI_SCK 70 +#set_io SPI_SI 68 +#set_io SPI_SO 67 +#set_io SPI_SS_B 71 + +# Configuration pins +#set_io CDONE 65 +#set_io CRESET_B 66 + +# 12 MHz clock +set_io CLK 21 diff --git a/flash.v b/flash.v index 633cf6a..7168053 100644 --- a/flash.v +++ b/flash.v @@ -1,96 +1,16 @@ `include "processor_4.v" -module top (input CLK, output [7:0] OUT_C, output [2:0] OUT_R, output [3:0] IN_C, input [3:0] IN_R, output [3:0] IND, output UART_TX, input UART_RX); - - wire [23:0] led; - - // Prescaler on the clock - - reg [24:0] counter = 0; - - always @ (posedge CLK) begin - - counter <= counter + 1; - - end - - // Handle the inputs - - reg [3:0] shift_in = 4'b1110; - - always @ (negedge counter[13]) begin - - shift_in <= { shift_in[2:0], shift_in[3] }; - - end - - assign IN_C = shift_in; - - reg [15:0] buttons = 0; - - always @ (posedge counter[13]) begin - - case (shift_in) - 4'b1110: begin - buttons[0] <= !IN_R[0]; - buttons[4] <= !IN_R[1]; - buttons[8] <= !IN_R[2]; - buttons[12] <= !IN_R[3]; - end - 4'b1101: begin - buttons[1] <= !IN_R[0]; - buttons[5] <= !IN_R[1]; - buttons[9] <= !IN_R[2]; - buttons[13] <= !IN_R[3]; - end - 4'b1011: begin - buttons[2] <= !IN_R[0]; - buttons[6] <= !IN_R[1]; - buttons[10] <= !IN_R[2]; - buttons[14] <= !IN_R[3]; - end - 4'b0111: begin - buttons[3] <= !IN_R[0]; - buttons[7] <= !IN_R[1]; - buttons[11] <= !IN_R[2]; - buttons[15] <= !IN_R[3]; - end - endcase - - end - - // Connect up the processor - - PROCESSOR cpu(.clk(CLK),//counter[20]), - .led(led), - .indicators(IND), - .uart_tx(UART_TX), - .uart_rx(UART_RX), - .buttons(buttons)); - - // Handle output stuff - - reg [7:0] out; - - reg [2:0] shift_out = 3'b001; - - always @ (posedge counter[7]) begin - - if (shift_out[2] == 1) - out <= led[7:0]; - if (shift_out[0] == 1) - out <= led[15:8]; - if (shift_out[1] == 1) - out <= led[23:16]; - - shift_out <= { shift_out[1:0], shift_out[2] }; +module top (input CLK, output [4:0] LED, output UART_TX, input UART_RX); + // Prescaler on the clock + reg [24:0] counter = 0; + always @ (posedge CLK) begin + counter <= counter + 1; end - assign OUT_R = shift_out; - - assign OUT_C = out; - -endmodule - - + // Connect up the processor + PROCESSOR cpu(.clk(counter[10]), + .led(LED), + .uart_tx(UART_TX), + .uart_rx(UART_RX)); +endmodule diff --git a/gc.v b/gc.v index b840205..64eb8fa 100644 --- a/gc.v +++ b/gc.v @@ -1,7 +1,7 @@ module GC (input clk, input mclk, input [7:0] Ein, output [7:0] Eout, input [3:0] gcop, output [5:0] ostate, output step_eval); reg [5:0] gostate = 6'o2; reg [5:0] gnstate; - reg [16:0] rom_output; + reg [15:0] rom_output; reg [7:0] Ein_latched; always @(posedge clk) begin diff --git a/prescaler.v b/prescaler.v index 368a94f..86a445f 100644 --- a/prescaler.v +++ b/prescaler.v @@ -1,15 +1,11 @@ // Prescalar with default 16 bit division module PRESCALER #(parameter BITS = 16) (input clk, output out); - reg [BITS-1:0] counter = 0; - - always @ (posedge clk) begin - + + always @ (posedge clk) begin counter <= counter + 1; - end assign out = counter[BITS-1]; - endmodule diff --git a/processor_4.v b/processor_4.v index 2184846..aa894bf 100644 --- a/processor_4.v +++ b/processor_4.v @@ -23,15 +23,6 @@ `define INST_CAR 4'b1111 `define INST_CDR 4'b1101 -`define STORE_BUTTON buttons[8] -`define CLEAR_BUTTON buttons[9] -`define PC_INC_BUTTON buttons[10] -`define PC_DEC_BUTTON buttons[11] -`define PC_CLR_BUTTON buttons[12] -`define ACCUM_CLR_BUTTON buttons[13] -`define RUN_BUTTON buttons[14] -`define EXECUTE_BUTTON buttons[15] - `define GCOP_NOP 4'd0 `define GCOP_CDR 4'd1 `define GCOP_CAR 4'd2 @@ -52,7 +43,7 @@ // This is a simple four bit accumulator machine. It is a Havard architecture with separate // program and user memory address spaces. -module PROCESSOR (input clk, output [23:0] led, output [3:0] indicators, input [15:0] buttons, output uart_tx, input uart_rx); +module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx); // storage unit reg [7:0] Ein; wire [7:0] Eout; @@ -66,31 +57,14 @@ module PROCESSOR (input clk, output [23:0] led, output [3:0] indicators, input [ reg running = 1; - always @ (posedge `RUN_BUTTON) begin - running <= !running; - end - - // Generate running clock - - wire running_counter; - - PRESCALER #(.BITS(1)) scal0 (.clk(clk), .out(running_counter)); - - wire running_clk = running & running_counter; - - // Handle execution - - wire execute_trigger; + // Generate eval and gc clocks - SINGLE_TRIGGER trig0 (.clk(clk), .trigger_in(`EXECUTE_BUTTON), .trigger_out(execute_trigger)); - - wire running_trigger; - - SINGLE_TRIGGER trig1 (.clk(clk), .trigger_in(running_clk), .trigger_out(running_trigger)); - - wire gc_clock = (!running & execute_trigger) | running_clk; + reg gc_clock = 0; wire eval_clock = !gc_clock & step_eval; + always @ (posedge clk) + gc_clock <= !gc_clock; + GC gc (.clk(gc_clock), .mclk(clk), .Ein(Ein), .Eout(Eout), .gcop(gcop), .ostate(ostate), .step_eval(step_eval)); // Handle halt @@ -156,14 +130,6 @@ module PROCESSOR (input clk, output [23:0] led, output [3:0] indicators, input [ wire [3:0] next = pc + 4'b0001; wire [3:0] prev = pc + 4'b1111; - wire pc_prev_trigger; - wire pc_next_trigger; - wire pc_zero_trigger; - - SINGLE_TRIGGER trig3 (.clk(clk), .trigger_in(`PC_INC_BUTTON), .trigger_out(pc_next_trigger)); - SINGLE_TRIGGER trig4 (.clk(clk), .trigger_in(`PC_DEC_BUTTON), .trigger_out(pc_prev_trigger)); - SINGLE_TRIGGER trig5 (.clk(clk), .trigger_in(`PC_CLR_BUTTON), .trigger_out(pc_zero_trigger)); - wire [3:0] newPc = (inst == `INST_JP) ? argu : (inst == `INST_JPZ) & (accum == 4'b0000) ? argu : @@ -172,9 +138,6 @@ module PROCESSOR (input clk, output [23:0] led, output [3:0] indicators, input [ (inst == `INST_READ) & !fifo_re ? pc : (inst == `INST_RDQ) & !reading_E ? pc : (inst != `INST_HALT) ? next : -/* !running & pc_zero_trigger ? 4'b00000 : - !running & pc_next_trigger ? next : - !running & pc_prev_trigger ? prev : */ pc; always @ (posedge eval_clock) begin @@ -208,8 +171,8 @@ module PROCESSOR (input clk, output [23:0] led, output [3:0] indicators, input [ hex_to_ascii h2a (.hex(accum), .ascii(uart_tx_byte)); - // 300-ish baud uart - uart #(.CLOCK_DIVIDE(81)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error)); + // 300 baud uart + uart #(.CLOCK_DIVIDE(5)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error)); // GC logic always @ (posedge eval_clock) begin @@ -249,16 +212,18 @@ module PROCESSOR (input clk, output [23:0] led, output [3:0] indicators, input [ assign led[4] = uart_rx_error; assign led[5] = fifo_empty; assign led[6] = fifo_full; - assign led[7] = fifo_re;*/ + assign led[7] = fifo_re; assign led[7:4] = Ein[3:0]; assign led[3:0] = Eout[3:0]; // assign led[15:8] = programOut; // assign led[15:8] = uart_rx_byte; - assign led[15] = step_eval; - assign led[14] = eval_clock; assign led[13:8] = ostate; assign led[19:16] = pc; assign led[23:20] = accum; - assign indicators = {1'b0, (!running & `EXECUTE_BUTTON) | running_clk, halt, running & !halt}; + assign indicators = {1'b0, (!running & `EXECUTE_BUTTON) | running_clk, halt, running & !halt};*/ + assign led[0] = eval_clock; + assign led[1] = uart_is_transmitting; + assign led[2] = uart_is_receiving; + assign led[3] = recv_error; endmodule diff --git a/rom.v b/rom.v index cd23054..b2aace7 100644 --- a/rom.v +++ b/rom.v @@ -5,7 +5,7 @@ module ROM (input clk, input [3:0] addr, output reg [7:0] data); always @ (posedge clk) begin case(addr) 4'd0: data <= 8'b0001_0110; // LDI 6 - 4'd1: data <= 8'b0110_1001; // JP 9 + 4'd1: data <= 8'b0110_0010; // JP 9 4'd2: data <= 8'b0010_0001; // ADD 1 4'd3: data <= 8'b1001_0000; // WRITE 4'd4: data <= 8'b0110_0010; // JP 2 @@ -23,6 +23,4 @@ module ROM (input clk, input [3:0] addr, output reg [7:0] data); default: data <= 8'bxxxx_xxxx; endcase end - - assign out_data = data_out_reg; endmodule