[clump.git] / master_rom.v

// ROM module with single input addr, output port, and clock input.
// Data is clocked out of the ROM on positive clock edges.

module master_rom (input clk, input [3:0] addr, output reg [31:0] data);
   always @ (posedge clk) begin
      case(addr)
0: data <= 32'h04000004;
1: data <= 32'h04010002;
2: data <= 32'h07010010;
3: data <= 32'h00000000;
4: data <= 32'h00000000;
5: data <= 32'h06000001;
6: data <= 32'h07010010;
7: data <= 32'h00000000;
8: data <= 32'h00000000;
9: data <= 32'h04010003;
10: data <= 32'h07010010;
11: data <= 32'h00000000;
12: data <= 32'h00000000;
13: data <= 32'h06000001;
14: data <= 32'h07010010;
15: data <= 32'h00000000;
	  endcase
   end
endmodule
Commit	Line	Data
3b542afc MG	1	// ROM module with single input addr, output port, and clock input.
	2	// Data is clocked out of the ROM on positive clock edges.
	3
7f1b6bd9	4	module master_rom (input clk, input [3:0] addr, output reg [31:0] data);
3b542afc MG	5	always @ (posedge clk) begin
3b542afc MG	6	case(addr)
7f1b6bd9 MG	7	0: data <= 32'h04000004;
	8	1: data <= 32'h04010002;
	9	2: data <= 32'h07010010;
	10	3: data <= 32'h00000000;
	11	4: data <= 32'h00000000;
	12	5: data <= 32'h06000001;
	13	6: data <= 32'h07010010;
	14	7: data <= 32'h00000000;
	15	8: data <= 32'h00000000;
	16	9: data <= 32'h04010003;
	17	10: data <= 32'h07010010;
	18	11: data <= 32'h00000000;
	19	12: data <= 32'h00000000;
	20	13: data <= 32'h06000001;
	21	14: data <= 32'h07010010;
	22	15: data <= 32'h00000000;
3b542afc MG	23	endcase
	24	end
	25	endmodule