[clump.git] / ram.v

module RAM #(parameter ADDRESS_BITS = 4)
(input clk, input write, input[ADDRESS_BITS-1:0] addr, input [15:0] in, output reg [15:0] out);

    reg [15:0] memory [0:2**ADDRESS_BITS-1];

    always @ (negedge clk) begin
        if (write)
		  memory[addr] <= in;
        out <= memory[addr];
    end
endmodule
Commit	Line	Data
5a2a82dc MG	1	module RAM #(parameter ADDRESS_BITS = 4)
5a2a82dc MG	2	(input clk, input write, input[ADDRESS_BITS-1:0] addr, input [15:0] in, output reg [15:0] out);
a051754e	3
5a2a82dc	4	reg [15:0] memory [0:2**ADDRESS_BITS-1];
a051754e	5
5a2a82dc MG	6	always @ (negedge clk) begin
	7	if (write)
	8	memory[addr] <= in;
	9	out <= memory[addr];
a051754e	10	end
a051754e	11	endmodule