Conway works (with sleeps)

[clump.git] / Makefile

diff --git a/Makefile b/Makefile
index 64606370a5316b756a95158e6f162cf6fe53d260..0fb0a575be3498fa5c8ebb7dc58637598ad34449 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -22,4 +22,8 @@ prog: $(PROJ).bin
 clean:
        rm -f $(PROJ).blif $(PROJ).asc $(PROJ).bin
 
-.PHONY: all prog clean
+
+sim:
+       tools/yosys/yosys -p 'read_verilog -sv -DSIM toplevel.v; prep -top toplevel -nordff; sim -clock CLKin -vcd test.vcd -n 3000'
+
+.PHONY: all prog clean sim