Make it work

[clump.git] / Makefile

diff --git a/Makefile b/Makefile
index e2c55e51e8aeba470fb0bc42aa38029f57958b53..1b88b5cc067ba581b9a065663003807172feb444 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1,13 +1,17 @@
-PROJ = master
-PIN_DEF = master.pcf
 DEVICE = hx1k
 
-all: $(PROJ).rpt $(PROJ).bin
+all: toplevel.bin
 
-%.blif: %.v
+toplevel.bin: master.rpt master.bin worker.rpt worker.bin
+       tools/icestorm/icemulti/icemulti -o toplevel.bin -v -p0 worker.bin master.bin
+
+master.blif: master.v
        tools/yosys/yosys -p 'synth_ice40 -top master -blif $@' $<
 
-%.asc: $(PIN_DEF) %.blif
+worker.blif: worker.v
+       tools/yosys/yosys -p 'synth_ice40 -top worker -blif $@' $<
+
+%.asc: %.pcf %.blif
        tools/arachne-pnr/bin/arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^ -P tq144
 
 %.bin: %.asc
@@ -16,14 +20,20 @@ all: $(PROJ).rpt $(PROJ).bin
 %.rpt: %.asc
        tools/icestorm/icetime/icetime -C tools/icestorm/icebox/chipdb-$(subst hx,,$(subst lp,,$(DEVICE))).txt -d $(DEVICE) -mtr $@ $<
 
-prog: $(PROJ).bin
+prog: toplevel.bin
+       tools/icestorm/iceprog/iceprog $<
+
+progall: toplevel.bin
+       bash progall.sh
+
+progmaster: master.bin
        tools/icestorm/iceprog/iceprog $<
 
 clean:
-       rm -f $(PROJ).blif $(PROJ).asc $(PROJ).bin
+       rm -f master.blif master.asc worker.blif worker.asc master.bin worker.bin toplevel.bin
 
 
 sim:
-       tools/yosys/yosys -p 'read_verilog -sv -DSIM master.v; prep -top master -nordff; sim -clock CLKin -vcd test.vcd -n 3000'
+       tools/yosys/yosys -p 'read_verilog -sv -DSIM worker.v; prep -top worker -nordff; sim -clock CLKin -vcd test.vcd -n 3000'
 
 .PHONY: all prog clean sim