Discover the PLL and multiply the CLK by 4

[clump.git] / lisp_processor.v

diff --git a/lisp_processor.v b/lisp_processor.v
index f856aa2ada64a4652aec41c907272f7c6b6e7208..fbc44673d5f9961a5cb7b20e37ba3bfcc1b79cba 100644 (file)
--- a/lisp_processor.v
+++ b/lisp_processor.v
@@ -1,3 +1,4 @@
+`include "pll.v"
 `include "gc.v"
 `include "eval.v"
 `include "reader.v"
@@ -28,7 +29,11 @@
  `define UART_DIVIDE 625
 `endif
 
-module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx);
+module cpu (input CLKin, output [4:0] led, output uart_tx, input uart_rx);
+   wire clk;
+
+   pll pll (.clock_in(CLKin), .clock_out(clk));
+
    wire [12:0] freeptr;
    wire [15:0] E1;
    wire [15:0] E2;
@@ -88,6 +93,6 @@ module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx);
    wire          uart_tx_signal;
    wire [7:0] uart_tx_byte;
 
-   // 4800 baud uart
+   // 19200 baud uart
    uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error));
 endmodule