First version, probably does not work

[clump.git] / ram.v

diff --git a/ram.v b/ram.v
index a7e69fdba3fef648cea21853597b4df7face8bdd..372067543aa9f8de99ede34f79bd53d4962872ac 100644 (file)
--- a/ram.v
+++ b/ram.v
@@ -1,22 +1,11 @@
-// RAM module with single input addr, input and output ports, a write enable and clock input.
-// Data is clocked out of, and into, the RAM on positive clock edges.
+module RAM #(parameter ADDRESS_BITS = 4)
+(input clk, input write, input[ADDRESS_BITS-1:0] addr, input [15:0] in, output reg [15:0] out);
 
-module RAM #(parameter DATA_BITS = 8,  parameter ADDRESS_BITS = 4)
+    reg [15:0] memory [0:2**ADDRESS_BITS-1];
 
-(input clk, input write, input[ADDRESS_BITS-1:0] addr, input[DATA_BITS-1:0] in_data, output[DATA_BITS-1:0] out_data);
-   
-   reg [DATA_BITS-1:0] memorySpace [0:2**ADDRESS_BITS-1];                          
-
-   reg [DATA_BITS-1:0] data_out_reg;
-   
-   always @ (posedge clk) begin
-
-       if (write) memorySpace[addr] <= in_data;
-
-       data_out_reg <= memorySpace[addr];
-       
+    always @ (negedge clk) begin
+        if (write)
+                 memory[addr] <= in;
+        out <= memory[addr];
     end
-
-   assign out_data = data_out_reg;
-   
 endmodule