First version, probably does not work

[clump.git] / toplevel.v

diff --git a/toplevel.v b/toplevel.v
new file mode 100644 (file)
index 0000000..728fee4
--- /dev/null
+++ b/toplevel.v
@@ -0,0 +1,70 @@
+`include "ram.v"
+`include "chip.v"
+`include "uart.v"
+
+module toplevel (input CLKin, output [4:0] led, output uart_tx, input uart_rx);
+   wire clk = CLKin;
+
+   wire [11:0] mem_addr;
+   wire [15:0] mem_in;
+   wire [15:0] mem_out;
+   wire           mem_write;
+
+   RAM #(.ADDRESS_BITS(12)) ram (.clk(clk), .write(mem_write), .addr(mem_addr), .in(mem_in), .out(mem_out));
+
+   reg [7:0]   from_uart [3:0];
+   reg [2:0]   uart_ptr = 0;
+
+   wire [15:0] I  = {from_uart[1], from_uart[0]};
+   assign mem_addr = from_uart[2];
+   wire [2:0]  op_from_uart = from_uart[3][2:0];
+   wire           CS = from_uart[3][3];
+
+   reg [2:0]   op = 0;
+
+   assign led = uart_ptr;
+
+   chip chip (.clk(clk), .op(op), .I(I), .io_pin(0), .CS(CS), .mem_in(mem_in), .mem_out(mem_out), .mem_write(mem_write));
+
+   wire           received;
+   wire [7:0]  rx_byte;
+   reg                    transmit = 0;
+   reg  [7:0]  tx_byte;
+
+   uart uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .received(received), .transmit(transmit), .tx_byte(tx_byte), .rx_byte(rx_byte));
+
+   reg [15:0]  rom_I [0:5];
+   reg [7:0]  rom_mem_addr [0:5];
+   reg [2:0]  rom_op [0:5];
+   reg                   rom_CS [0:5];
+
+   reg [2:0]   state = 0;
+
+   always @ (posedge clk) begin
+         if (received) begin
+                from_uart[uart_ptr] <= rx_byte;
+                uart_ptr <= uart_ptr + 1;
+         end
+
+         if (uart_ptr == 4) begin
+                op <= op_from_uart;
+                uart_ptr <= 0;
+                state <= 1;
+         end
+
+         if (state == 1) begin
+                transmit <= 1;
+                tx_byte <= mem_in;
+                state <= 2;
+         end
+
+         if (state == 2) begin
+                transmit <= 0;
+                state <= 0;
+         end
+
+         if (op != 0) begin
+                op <= 0;
+         end
+   end
+endmodule