more speed

[clump.git] / worker.v

diff --git a/worker.v b/worker.v
index 9a7760e5d07f2f19eddfd00b4abfd25b869581c6..9e03d936f9a5a756fc8346e9c166b4e2fb8c272c 100644 (file)
--- a/worker.v
+++ b/worker.v
@@ -6,7 +6,7 @@
 `ifdef SIM
  `define UART_DIVIDE 1
 `else
- `define UART_DIVIDE 2048
+ `define UART_DIVIDE 1024
 `endif
 
 module worker (input CLKin, output [4:0] led, output uart_tx, input uart_rx, output reg busy_out = 1, input busy_in, input is_worker);
@@ -24,7 +24,7 @@ module worker (input CLKin, output [4:0] led, output uart_tx, input uart_rx, out
 
    always @(posedge clk) begin
          if(busy_in)
-               dont_send <= 23'b11111111111111111111111;
+               dont_send <= 21'b111111111111111111111;
          else if(dont_send)
                dont_send <= dont_send - 1;
    end