Better writer and faster UART

[yule.git] / reader.v

diff --git a/reader.v b/reader.v
index 8386b532367d7971bc291633f01554afbad29357..2f06a8466b15bb4d4f8a5d00bcda2b382bf75c40 100644 (file)
--- a/reader.v
+++ b/reader.v
@@ -6,7 +6,7 @@
 module READER (input clk, input clk_enable, input [7:0] uart_rx_byte, input uart_rx_signal, input uart_is_receiving, output reg active, output reg ram_we, output [12:0] ram_addr, output reg [15:0] ram_di);
    reg [1:0] state = `STATE_IDLE;
 
-   reg [12:0] bytes_left = 0;
+   reg [12:0] words_left = 0;
    reg [12:0] current_index = 0;
 
    assign ram_addr = current_index;
@@ -18,8 +18,8 @@ module READER (input clk, input clk_enable, input [7:0] uart_rx_byte, input uart
                case(state)
                  `STATE_IDLE: begin
                         if(uart_rx_signal) begin
-                               bytes_left[12:8] <= uart_rx_byte[4:0];
-                               bytes_left[7:0] <= 0;
+                               words_left[12:8] <= uart_rx_byte[4:0];
+                               words_left[7:0] <= 0;
                                current_index <= -1;
                                active <= 1;
                                state <= `STATE_LENGTH;
@@ -29,7 +29,7 @@ module READER (input clk, input clk_enable, input [7:0] uart_rx_byte, input uart
 
                  `STATE_LENGTH: begin
                         if(uart_rx_signal) begin
-                               bytes_left[7:0] <= uart_rx_byte;
+                               words_left[7:0] <= uart_rx_byte;
                                state <= `STATE_READ1;
                         end
                  end
@@ -38,7 +38,7 @@ module READER (input clk, input clk_enable, input [7:0] uart_rx_byte, input uart
                         if(uart_rx_signal) begin
                                ram_di[15:8] <= uart_rx_byte;
                                current_index <= current_index + 1;
-                               bytes_left <= bytes_left - 1;
+                               words_left <= words_left - 1;
                                state <= `STATE_READ2;
                         end
                  end
@@ -47,7 +47,7 @@ module READER (input clk, input clk_enable, input [7:0] uart_rx_byte, input uart
                         if(uart_rx_signal) begin
                                ram_di[7:0] <= uart_rx_byte;
                                ram_we <= 1;
-                               state <= |bytes_left ? `STATE_READ1 : `STATE_IDLE;
+                               state <= |words_left ? `STATE_READ1 : `STATE_IDLE;
                         end
                  end
                endcase