`define STATE_WRITE2 2'b10
`define STATE_INCREMENT 2'b11
-module WRITER (input clk, input clk_enable, output reg [7:0] tx_byte, output reg tx_signal = 0, input tx_busy, output reg finished = 0, output [12:0] ram_addr, input [15:0] ram_do, input [12:0] P);
+module WRITER (input clk, input clk_enable, output reg [7:0] tx_byte, output reg tx_signal = 0, input tx_busy, output reg finished = 0, output [12:0] ram_addr, input [15:0] ram_do, input [12:0] freeptr);
reg [1:0] state = `STATE_START;
reg [12:0] current_index;
- reg [12:0] freeptr;
assign ram_addr = current_index;
case(state)
`STATE_START: begin
- finished <= 0;
current_index <= 4;
- freeptr <= P;
state <= `STATE_WRITE1;
end