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Commit | Line | Data |
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2ed306f8 | 1 | module GCRAM |
b5efed3a MG |
2 | (input clk, input we, input[12:0] addr, input[15:0] di, output reg [15:0] do, output reg [15:0] result); |
3 | reg [15:0] mem [255:0]; | |
2ed306f8 MG |
4 | |
5 | always @ (posedge clk) | |
6 | do <= #1 mem[addr]; | |
7 | ||
8 | always @ (posedge clk) | |
9 | if (we) | |
10 | mem[addr] <= #1 di; | |
11 | ||
12 | always @ (posedge clk) | |
13 | result <= mem[6]; | |
14 | ||
15 | initial begin | |
ab3ea03d MG |
16 | mem[ 0] <= 0; // (cdr part of NIL) |
17 | mem[ 1] <= 0; // (car part of NIL) | |
18 | mem[ 2] <= 16'b0010000000000000; // (cdr part of T) | |
19 | mem[ 3] <= 16'b0010000000000000; // (car part of T) | |
20 | mem[ 4] <= 16'd12; // (free storage pointer) | |
21 | mem[ 5] <= 16'b1100000000000111; // CALL 7 | |
22 | mem[ 6] <= 0; // (result of computation) | |
23 | mem[ 7] <= 16'b0000000000001001; // MORE 9 | |
24 | mem[ 8] <= 16'b0010000000000101; // NUMBER 5 | |
25 | mem[ 9] <= 16'b1110000000000000; // FUNCALL NIL | |
26 | mem[10] <= 16'b1000000000001011; // PROC 11 | |
27 | mem[11] <= 16'b0101111111111110; // VAR -2 | |
2ed306f8 MG |
28 | end |
29 | endmodule |