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Commit | Line | Data |
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3e7694a3 | 1 | `include "pll.v" |
2ed306f8 MG |
2 | `include "gc.v" |
3 | `include "eval.v" | |
3f6eb730 | 4 | `include "reader.v" |
2ed306f8 | 5 | `include "uart.v" |
3f6eb730 | 6 | `include "writer.v" |
08f23977 | 7 | `include "controller.v" |
2ed306f8 MG |
8 | |
9 | `define GCOP_NOP 4'd0 | |
10 | `define GCOP_CDR 4'd1 | |
11 | `define GCOP_CAR 4'd2 | |
12 | `define GCOP_CDRQ 4'd3 | |
13 | `define GCOP_CARQ 4'd4 | |
14 | `define GCOP_CARR 4'd5 | |
15 | `define GCOP_CDRRX 4'd6 | |
16 | `define GCOP_CARRX 4'd7 | |
17 | `define GCOP_CDRQX 4'd8 | |
18 | `define GCOP_CONS 4'd9 | |
19 | `define GCOP_XCONS 4'd10 | |
20 | `define GCOP_RPLACDR 4'd11 | |
21 | `define GCOP_LDQ 4'd12 | |
22 | `define GCOP_RDQ 4'd13 | |
23 | `define GCOP_RDQA 4'd14 | |
24 | `define GCOP_RDQCDRRX 4'd15 | |
25 | ||
3f6eb730 MG |
26 | `ifdef SIM |
27 | `define UART_DIVIDE 1 | |
28 | `else | |
a2b596a6 | 29 | `define UART_DIVIDE 3 |
3f6eb730 MG |
30 | `endif |
31 | ||
3e7694a3 MG |
32 | module cpu (input CLKin, output [4:0] led, output uart_tx, input uart_rx); |
33 | wire clk; | |
34 | ||
35 | pll pll (.clock_in(CLKin), .clock_out(clk)); | |
36 | ||
6414d51a | 37 | wire [12:0] freeptr; |
b5efed3a MG |
38 | wire [15:0] E1; |
39 | wire [15:0] E2; | |
2ed306f8 MG |
40 | wire [3:0] gcop; |
41 | wire [5:0] gostate; | |
42 | wire [5:0] eostate; | |
43 | wire conn_ea; | |
44 | wire conn_et; | |
45 | ||
46 | wire step_eval; | |
47 | ||
3f6eb730 MG |
48 | wire gc_ram_we; |
49 | wire [12:0] gc_ram_addr; | |
50 | wire [15:0] gc_ram_di; | |
51 | ||
52 | wire reader_ram_we; | |
53 | wire [12:0] reader_ram_addr; | |
54 | wire [15:0] reader_ram_di; | |
55 | ||
56 | wire [12:0] writer_ram_addr; | |
57 | ||
08f23977 MG |
58 | wire ram_we; |
59 | wire [12:0] ram_addr; | |
60 | wire [15:0] ram_di; | |
44b73af5 MG |
61 | wire [15:0] ram_do; |
62 | ||
08f23977 | 63 | wire eval_finished; |
62e5ccb8 | 64 | wire reader_finished; |
3f6eb730 | 65 | wire writer_finished; |
3f6eb730 | 66 | |
08f23977 MG |
67 | wire gc_clock_enable; |
68 | wire eval_clock_enable; | |
69 | wire reader_clock_enable; | |
70 | wire writer_clock_enable; | |
71 | wire reset; | |
72 | ||
73 | CTRL ctrl (.clk(clk), .step_eval(step_eval), .reader_finished(reader_finished), .eval_finished(eval_finished), .writer_finished(writer_finished), .gc_clock_enable(gc_clock_enable), .eval_clock_enable(eval_clock_enable), .reader_clock_enable(reader_clock_enable), .writer_clock_enable(writer_clock_enable), .reset(reset), .gc_ram_we(gc_ram_we), .reader_ram_we(reader_ram_we), .gc_ram_addr(gc_ram_addr), .reader_ram_addr(reader_ram_addr), .writer_ram_addr(writer_ram_addr), .gc_ram_di(gc_ram_di), .reader_ram_di(reader_ram_di), .ram_we(ram_we), .ram_addr(ram_addr), .ram_di(ram_di), .uart_is_receiving(uart_is_receiving), .uart_is_transmitting(uart_is_transmitting), .led(led)); | |
74 | ||
eb54e6d0 | 75 | GCRAM gcram (.clk(clk), .we(ram_we), .addr(ram_addr), .di(ram_di), .do(ram_do)); |
44b73af5 | 76 | |
b0d6183f | 77 | GC gc (.clk(clk), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(gc_ram_we), .ram_addr(gc_ram_addr), .ram_di(gc_ram_di), .ram_do(ram_do), .freeptr(freeptr)); |
3f6eb730 | 78 | |
08f23977 | 79 | EVAL eval (.clk(clk), .rst(reset), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et), .eval_finished(eval_finished)); |
2ed306f8 | 80 | |
62e5ccb8 | 81 | READER reader (.clk(clk), .clk_enable(reader_clock_enable), .rx_byte(uart_rx_byte), .rx_signal(uart_rx_signal), .finished(reader_finished), .ram_we(reader_ram_we), .ram_addr(reader_ram_addr), .ram_di(reader_ram_di)); |
3f6eb730 | 82 | |
6414d51a | 83 | WRITER writer (.clk(clk), .clk_enable(writer_clock_enable), .tx_byte(uart_tx_byte), .tx_signal(uart_tx_signal), .tx_busy(uart_is_transmitting), .finished(writer_finished), .ram_addr(writer_ram_addr), .ram_do(ram_do), .freeptr(freeptr)); |
2ed306f8 MG |
84 | |
85 | // UART outputs | |
86 | wire uart_rx_signal; | |
87 | wire [7:0] uart_rx_byte; | |
88 | wire uart_is_receiving; | |
89 | wire uart_is_transmitting; | |
90 | wire uart_rx_error; | |
91 | ||
2ed306f8 | 92 | // UART logic |
3f6eb730 MG |
93 | wire uart_tx_signal; |
94 | wire [7:0] uart_tx_byte; | |
95 | ||
3e7694a3 | 96 | // 19200 baud uart |
3f6eb730 | 97 | uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error)); |
2ed306f8 | 98 | endmodule |