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Commit | Line | Data |
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a051754e MG |
1 | // Take variable duration pulse which may be high at any time and generate multiple cycle |
2 | // high pulses alligned with the positive edge of the clock pulse. | |
3 | ||
4 | module MULTIPLE_TRIGGER #(parameter BITS = 4) (input clk, input trigger_in, output[BITS-1:0] trigger_out); | |
5 | ||
6 | reg [BITS-1:0] trigger = 0; | |
7 | ||
8 | reg last_trigger_in = 0; | |
9 | ||
10 | always @ (posedge clk) begin | |
11 | ||
12 | trigger <= { trigger[BITS-2:0], (!last_trigger_in & trigger_in) }; | |
13 | ||
14 | last_trigger_in <= trigger_in; | |
15 | ||
16 | end | |
17 | ||
18 | assign trigger_out = trigger; | |
19 | ||
20 | endmodule |