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1 | `include "processor_4.v" | |
2 | ||
3 | module top (input CLK, output [7:0] OUT_C, output [2:0] OUT_R, output [3:0] IN_C, input [3:0] IN_R, output [3:0] IND, output UART_TX, input UART_RX); | |
4 | ||
5 | wire [23:0] led; | |
6 | ||
7 | // Prescaler on the clock | |
8 | ||
9 | reg [24:0] counter = 0; | |
10 | ||
11 | always @ (posedge CLK) begin | |
12 | ||
13 | counter <= counter + 1; | |
14 | ||
15 | end | |
16 | ||
17 | // Handle the inputs | |
18 | ||
19 | reg [3:0] shift_in = 4'b1110; | |
20 | ||
21 | always @ (negedge counter[13]) begin | |
22 | ||
23 | shift_in <= { shift_in[2:0], shift_in[3] }; | |
24 | ||
25 | end | |
26 | ||
27 | assign IN_C = shift_in; | |
28 | ||
29 | reg [15:0] buttons = 0; | |
30 | ||
31 | always @ (posedge counter[13]) begin | |
32 | ||
33 | case (shift_in) | |
34 | 4'b1110: begin | |
35 | buttons[0] <= !IN_R[0]; | |
36 | buttons[4] <= !IN_R[1]; | |
37 | buttons[8] <= !IN_R[2]; | |
38 | buttons[12] <= !IN_R[3]; | |
39 | end | |
40 | 4'b1101: begin | |
41 | buttons[1] <= !IN_R[0]; | |
42 | buttons[5] <= !IN_R[1]; | |
43 | buttons[9] <= !IN_R[2]; | |
44 | buttons[13] <= !IN_R[3]; | |
45 | end | |
46 | 4'b1011: begin | |
47 | buttons[2] <= !IN_R[0]; | |
48 | buttons[6] <= !IN_R[1]; | |
49 | buttons[10] <= !IN_R[2]; | |
50 | buttons[14] <= !IN_R[3]; | |
51 | end | |
52 | 4'b0111: begin | |
53 | buttons[3] <= !IN_R[0]; | |
54 | buttons[7] <= !IN_R[1]; | |
55 | buttons[11] <= !IN_R[2]; | |
56 | buttons[15] <= !IN_R[3]; | |
57 | end | |
58 | endcase | |
59 | ||
60 | end | |
61 | ||
62 | // Connect up the processor | |
63 | ||
64 | PROCESSOR cpu(.clk(CLK),//counter[20]), | |
65 | .led(led), | |
66 | .indicators(IND), | |
67 | .uart_tx(UART_TX), | |
68 | .uart_rx(UART_RX), | |
69 | .buttons(buttons)); | |
70 | ||
71 | // Handle output stuff | |
72 | ||
73 | reg [7:0] out; | |
74 | ||
75 | reg [2:0] shift_out = 3'b001; | |
76 | ||
77 | always @ (posedge counter[7]) begin | |
78 | ||
79 | if (shift_out[2] == 1) | |
80 | out <= led[7:0]; | |
81 | if (shift_out[0] == 1) | |
82 | out <= led[15:8]; | |
83 | if (shift_out[1] == 1) | |
84 | out <= led[23:16]; | |
85 | ||
86 | shift_out <= { shift_out[1:0], shift_out[2] }; | |
87 | ||
88 | end | |
89 | ||
90 | assign OUT_R = shift_out; | |
91 | ||
92 | assign OUT_C = out; | |
93 | ||
94 | endmodule | |
95 | ||
96 |