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Commit | Line | Data |
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1 | module GCRAM | |
2 | (input clk, input we, input[5:0] addr, input[7:0] di, output reg [7:0] do, output reg [7:0] result); | |
3 | reg [7:0] mem [(1<<5)-1:0]; | |
4 | ||
5 | always @ (posedge clk) | |
6 | do <= #1 mem[addr]; | |
7 | ||
8 | always @ (posedge clk) | |
9 | if (we) | |
10 | mem[addr] <= #1 di; | |
11 | ||
12 | always @ (posedge clk) | |
13 | result <= mem[6]; | |
14 | ||
15 | initial begin | |
16 | mem[0] <= 0; | |
17 | mem[1] <= 0; | |
18 | mem[2] <= 8'b00100000; | |
19 | mem[3] <= 8'b00100000; | |
20 | mem[4] <= 8'd8; | |
21 | mem[5] <= 8'b11101000; /* QUOTE 8 */ | |
22 | mem[6] <= 0; | |
23 | mem[7] <= 8'd49; | |
24 | mem[8] <= 8'd49; | |
25 | mem[9] <= 8'd49; | |
26 | end | |
27 | endmodule |