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Commit | Line | Data |
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1 | // Prescalar with default 16 bit division | |
2 | ||
3 | module PRESCALER #(parameter BITS = 16) (input clk, output out); | |
4 | reg [BITS-1:0] counter = 0; | |
5 | ||
6 | always @ (posedge clk) begin | |
7 | counter <= counter + 1; | |
8 | end | |
9 | ||
10 | assign out = counter[BITS-1]; | |
11 | endmodule |