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Commit | Line | Data |
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1 | module RAM #(parameter ADDRESS_BITS = 4) | |
2 | (input clk, input write, input[ADDRESS_BITS-1:0] addr, input [15:0] in, output reg [15:0] out); | |
3 | ||
4 | reg [15:0] memory [0:2**ADDRESS_BITS-1]; | |
5 | ||
6 | reg [ADDRESS_BITS:0] idx; | |
7 | initial begin | |
8 | for(idx = 0; idx < 2**ADDRESS_BITS; idx=idx+1) | |
9 | memory[idx] <= 0; | |
10 | end | |
11 | ||
12 | always @ (negedge clk) begin | |
13 | if (write) | |
14 | memory[addr] <= in; | |
15 | out <= memory[addr]; | |
16 | end | |
17 | endmodule |