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Commit | Line | Data |
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1 | `define STATE_IDLE 3'd0 | |
2 | `define STATE_LENGTH 3'd1 | |
3 | `define STATE_READ1 3'd2 | |
4 | `define STATE_READ2 3'd3 | |
5 | `define STATE_WRITE 3'd4 | |
6 | `define STATE_FINISHED 3'd5 | |
7 | ||
8 | module READER (input clk, input clk_enable, input [7:0] rx_byte, input rx_signal, output finished, output ram_we, output [12:0] ram_addr, output reg [15:0] ram_di); | |
9 | reg [2:0] state = `STATE_IDLE; | |
10 | ||
11 | reg [12:0] total_words; | |
12 | reg [12:0] current_index; | |
13 | ||
14 | assign ram_addr = current_index; | |
15 | assign finished = state == `STATE_FINISHED; | |
16 | assign ram_we = state == `STATE_WRITE; | |
17 | ||
18 | always @ (posedge clk) | |
19 | if (clk_enable) begin | |
20 | case(state) | |
21 | `STATE_IDLE: begin | |
22 | if(rx_signal) begin | |
23 | total_words[12:8] <= rx_byte[4:0]; | |
24 | current_index <= -1; | |
25 | state <= `STATE_LENGTH; | |
26 | end | |
27 | end | |
28 | ||
29 | `STATE_LENGTH: begin | |
30 | if(rx_signal) begin | |
31 | total_words[7:0] <= rx_byte; | |
32 | state <= `STATE_READ1; | |
33 | end | |
34 | end | |
35 | ||
36 | `STATE_READ1: begin | |
37 | if(rx_signal) begin | |
38 | ram_di[15:8] <= rx_byte; | |
39 | current_index <= current_index + 1; | |
40 | state <= `STATE_READ2; | |
41 | end | |
42 | end | |
43 | ||
44 | `STATE_READ2: begin | |
45 | if(rx_signal) begin | |
46 | ram_di[7:0] <= rx_byte; | |
47 | state <= `STATE_WRITE; | |
48 | end | |
49 | end | |
50 | ||
51 | `STATE_WRITE: begin | |
52 | if(current_index + 1 == total_words) begin | |
53 | state <= `STATE_FINISHED; | |
54 | end else begin | |
55 | state <= `STATE_READ1; | |
56 | end | |
57 | end | |
58 | ||
59 | `STATE_FINISHED: state <= `STATE_IDLE; | |
60 | default: state <= `STATE_IDLE; | |
61 | endcase | |
62 | end // if (clk_enable) | |
63 | endmodule |