]> iEval git - clump.git/blame_incremental - yosys-sim-script
Discover the PLL and multiply the CLK by 4
[clump.git] / yosys-sim-script
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1read_verilog -sv -DSIM lisp_processor.v
2prep -top cpu -nordff
3sim -clock clk -vcd test.vcd -n 3000
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