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iEval git - yule.git/blame_incremental - yosys-sim-script
... / ...
Commit | Line | Data |
| 1 | read_verilog -sv -DSIM lisp_processor.v |
| 2 | prep -top cpu -nordff |
| 3 | sim -clock clk -vcd test.vcd -n 3000 |
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