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1 `include "gcram.v"
2
3 module GC (input clk, input clk_enable, input rst, input [15:0] Ein, output [15:0] Eout, input [3:0] gcop, output [5:0] ostate, output conn_et, output conn_ea, output step_eval, output ram_we, output [12:0] ram_addr, output [15:0] ram_di, input [15:0] ram_do, output [12:0] freeptr);
4 reg [15:0] rom_output;
5 reg [5:0] gostate;
6 reg [5:0] gnstate;
7
8 `ifdef SIM
9 initial begin
10 gostate <= 0;
11 end
12 `endif
13
14 wire ga_zero_disp = rom_output[15];
15 wire gcop_disp = rom_output[14];
16 assign ram_we = rom_output[13];
17 wire adr = rom_output[12];
18 wire rdR = rom_output[11];
19 wire rdQ = rom_output[10];
20 wire rdP_plus = rom_output[9];
21 wire rdP = rom_output[8];
22 wire ldS = rom_output[7];
23 wire ldR = rom_output[6];
24 wire ldQ = rom_output[5];
25 wire ldP = rom_output[4];
26 wire conn_i = rom_output[3];
27 assign conn_et = rom_output[2];
28 assign conn_ea = rom_output[1];
29 assign step_eval = rom_output[0];
30
31 wire ga_zero = ~|G[12:0];
32
33 always @* begin
34 case(gostate)
35 6'o00: begin rom_output <= 16'o010242; gnstate <= 6'o01; end
36 6'o01: begin rom_output <= 16'o000031; gnstate <= 6'o02; end
37 6'o02: begin rom_output <= 16'o040000; gnstate <= 6'o20; end
38 6'o03: begin rom_output <= 16'o000126; gnstate <= 6'o04; end
39 6'o04: begin rom_output <= 16'o001200; gnstate <= 6'o05; end
40 6'o05: begin rom_output <= 16'o002020 | (1 << 12); gnstate <= 6'o06; end
41 6'o06: begin rom_output <= 16'o000051; gnstate <= 6'o02; end
42 6'o07: begin rom_output <= 16'o002020; gnstate <= 6'o10; end
43 6'o10: begin rom_output <= 16'o001200; gnstate <= 6'o11; end
44 6'o11: begin rom_output <= 16'o004020; gnstate <= 6'o12; end
45 6'o12: begin rom_output <= 16'o002100 | (1 << 12); gnstate <= 6'o13; end
46 6'o13: begin rom_output <= 16'o000057; gnstate <= 6'o02; end
47 6'o14: begin rom_output <= 16'o004020; gnstate <= 6'o04; end
48 6'o15: begin rom_output <= 16'o000246; gnstate <= 6'o16; end
49 6'o16: begin rom_output <= 16'o020001; gnstate <= 6'o02; end
50 6'o17: begin rom_output <= 16'o002100; gnstate <= 6'o42; end
51 6'o20: begin rom_output <= 16'o000001; gnstate <= 6'o02; end
52 6'o21: begin rom_output <= 16'o010306; gnstate <= 6'o06; end
53 6'o22: begin rom_output <= 16'o000440; gnstate <= 6'o03; end
54 6'o23: begin rom_output <= 16'o012200; gnstate <= 6'o12; end
55 6'o24: begin rom_output <= 16'o000500; gnstate <= 6'o07; end
56 6'o25: begin rom_output <= 16'o004040; gnstate <= 6'o24; end
57 6'o26: begin rom_output <= 16'o014200; gnstate <= 6'o06; end
58 6'o27: begin rom_output <= 16'o000440; gnstate <= 6'o14; end
59 6'o30: begin rom_output <= 16'o012300; gnstate <= 6'o06; end
60 6'o31: begin rom_output <= 16'o111300; gnstate <= 6'o44; end
61 6'o32: begin rom_output <= 16'o111300; gnstate <= 6'o40; end
62 6'o33: begin rom_output <= 16'o014200; gnstate <= 6'o15; end
63 6'o34: begin rom_output <= 16'o000047; gnstate <= 6'o02; end
64 6'o35: begin rom_output <= 16'o002007; gnstate <= 6'o02; end
65 6'o36: begin rom_output <= 16'o002003; gnstate <= 6'o02; end
66 6'o37: begin rom_output <= 16'o014200; gnstate <= 6'o55; end
67 6'o40: begin rom_output <= 16'o004020; gnstate <= 6'o17; end
68 6'o41: begin rom_output <= 16'o000000; gnstate <= 6'o41; end
69 6'o42: begin rom_output <= 16'o000206; gnstate <= 6'o47; end
70 6'o43: begin rom_output <= 16'o000106; gnstate <= 6'o46; end
71 6'o44: begin rom_output <= 16'o004020; gnstate <= 6'o43; end
72 6'o45: begin rom_output <= 16'o000000; gnstate <= 6'o41; end
73 6'o46: begin rom_output <= 16'o002200; gnstate <= 6'o47; end
74 6'o47: begin rom_output <= 16'o020440; gnstate <= 6'o50; end
75 6'o50: begin rom_output <= 16'o111200; gnstate <= 6'o52; end
76 6'o51: begin rom_output <= 16'o021100; gnstate <= 6'o54; end
77 6'o52: begin rom_output <= 16'o004200; gnstate <= 6'o51; end
78 6'o53: begin rom_output <= 16'o000000; gnstate <= 6'o41; end
79 6'o54: begin rom_output <= 16'o004021; gnstate <= 6'o02; end
80 6'o55: begin rom_output <= 16'o002100; gnstate <= 6'o56; end
81 6'o56: begin rom_output <= 16'o000050; gnstate <= 6'o57; end
82 6'o57: begin rom_output <= 16'o004007; gnstate <= 6'o02; end
83 default: begin rom_output <= 16'o040000; gnstate <= 6'o20; end
84 endcase; // case (gostate)
85 end // always @ *
86
87 always @ (posedge clk) begin
88 if(rst)
89 gostate <= 0;
90 if(clk_enable)
91 gostate <=
92 ga_zero_disp ? (gnstate | ga_zero) :
93 gcop_disp ? (gnstate | gcop) :
94 gnstate;
95 end // always @ (posedge clk)
96
97 assign ostate = gostate;
98
99 reg [12:0] P;
100 reg [15:0] Q;
101 reg [15:0] R;
102 reg [15:0] S;
103
104 reg [12:0] A; // latched address
105
106 assign freeptr = P;
107 assign ram_addr = A;
108 assign ram_di = S;
109
110 wire [15:0] G;
111 wire [15:0] Gout;
112
113 wire [15:0] GfromR = rdR ? R : 0;
114 wire [15:0] GfromQ = rdQ ? Q : 0;
115 wire [15:0] GfromP = rdP ? {3'b0, P} : 0;
116 wire [15:0] GfromP_plus = rdP_plus ? {3'b0, P + 1} : 0;
117 wire [15:0] GfromI = conn_i ? ram_do : 0;
118 wire [12:0] GAfromE = conn_ea ? Ein[12:0] : 0;
119 wire [2:0] GTfromE = conn_et ? Ein[15:13] : 0;
120 wire [15:0] GfromE = {GTfromE, GAfromE};
121
122 assign G = GfromR | GfromQ | GfromP | GfromP_plus | GfromI | GfromE;
123 assign Gout = GfromR | GfromQ | GfromP | GfromP_plus | GfromI;
124
125 assign Eout[12:0] = conn_ea ? Gout[12:0] : 0;
126 assign Eout[15:13] = conn_et ? Gout[15:13] : 0;
127
128 always @ (posedge clk) begin
129 if(clk_enable) begin
130 if (ldS) S = G;
131 if (ldP) P <= G[12:0];
132 if (ldR) R <= G;
133 if (ldQ) Q <= G;
134 if (adr) A <= S[12:0];
135 end
136 end
137 endmodule // GC
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