2 (input clk, input we, input[5:0] addr, input[7:0] di, output reg [7:0] do, output reg [7:0] result);
3 reg [7:0] mem [(1<<5)-1:0];
12 always @ (posedge clk)
18 mem[2] <= 8'b00100000;
19 mem[3] <= 8'b00100000;
21 mem[5] <= 8'b11101000; /* QUOTE 8 */