1 //////////////////////////////////////////////////////////////////////
3 //// Generic Dual-Port Synchronous RAM ////
5 //// This file is part of memory library available from ////
6 //// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
9 //// This block is a wrapper with common dual-port ////
10 //// synchronous memory interface for different ////
11 //// types of ASIC and FPGA RAMs. Beside universal memory ////
12 //// interface it also provides behavioral model of generic ////
13 //// dual-port synchronous RAM. ////
14 //// It also contains a fully synthesizeable model for FPGAs. ////
15 //// It should be used in all OPENCORES designs that want to be ////
16 //// portable accross different target technologies and ////
17 //// independent of target memory. ////
19 //// Supported ASIC RAMs are: ////
20 //// - Artisan Dual-Port Sync RAM ////
21 //// - Avant! Two-Port Sync RAM (*) ////
22 //// - Virage 2-port Sync RAM ////
24 //// Supported FPGA RAMs are: ////
25 //// - Generic FPGA (VENDOR_FPGA) ////
26 //// Tested RAMs: Altera, Xilinx ////
27 //// Synthesis tools: LeonardoSpectrum, Synplicity ////
28 //// - Xilinx (VENDOR_XILINX) ////
29 //// - Altera (VENDOR_ALTERA) ////
32 //// - fix Avant! ////
33 //// - add additional RAMs (VS etc) ////
36 //// - Richard Herveille, richard@asics.ws ////
37 //// - Damjan Lampret, lampret@opencores.org ////
39 //////////////////////////////////////////////////////////////////////
41 //// Copyright (C) 2000 Authors and OPENCORES.ORG ////
43 //// This source file may be used and distributed without ////
44 //// restriction provided that this copyright statement is not ////
45 //// removed from the file and that any derivative work contains ////
46 //// the original copyright notice and the associated disclaimer. ////
48 //// This source file is free software; you can redistribute it ////
49 //// and/or modify it under the terms of the GNU Lesser General ////
50 //// Public License as published by the Free Software Foundation; ////
51 //// either version 2.1 of the License, or (at your option) any ////
52 //// later version. ////
54 //// This source is distributed in the hope that it will be ////
55 //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
56 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
57 //// PURPOSE. See the GNU Lesser General Public License for more ////
60 //// You should have received a copy of the GNU Lesser General ////
61 //// Public License along with this source; if not, download it ////
62 //// from http://www.opencores.org/lgpl.shtml ////
64 //////////////////////////////////////////////////////////////////////
66 // CVS Revision History
68 // $Log: not supported by cvs2svn $
69 // Revision 1.2 2001/11/08 19:11:31 samg
70 // added valid checks to behvioral model
72 // Revision 1.1.1.1 2001/09/14 09:57:10 rherveille
74 // Files are now compliant to Altera & Xilinx memories.
75 // Memories are now compatible, i.e. drop-in replacements.
76 // Added synthesizeable generic FPGA description.
77 // Created "generic_memories" cvs entry.
79 // Revision 1.1.1.2 2001/08/21 13:09:27 damjan
80 // *** empty log message ***
82 // Revision 1.1 2001/08/20 18:23:20 damjan
85 // Revision 1.1 2001/08/09 13:39:33 lampret
88 // Revision 1.2 2001/07/30 05:38:02 lampret
89 // Adding empty directories required by HDL coding guidelines
93 //`include "timescale.v"
96 //`define VENDOR_XILINX
97 //`define VENDOR_ALTERA
100 // Generic synchronous dual-port RAM interface
101 rclk, rrst, rce, oe, raddr, do,
102 wclk, wrst, wce, we, waddr, di
106 // Default address and data buses width
108 parameter aw = 5; // number of bits in address-bus
109 parameter dw = 16; // number of bits in data-bus
112 // Generic synchronous double-port RAM interface
115 input rclk; // read clock, rising edge trigger
116 input rrst; // read port reset, active high
117 input rce; // read port chip enable, active high
118 input oe; // output enable, active high
119 input [aw-1:0] raddr; // read address
120 output [dw-1:0] do; // data output
123 input wclk; // write clock, rising edge trigger
124 input wrst; // write port reset, active high
125 input wce; // write port chip enable, active high
126 input we; // write enable, active high
127 input [aw-1:0] waddr; // write address
128 input [dw-1:0] di; // data input
136 // Instantiation synthesizeable FPGA memory
138 // This code has been tested using LeonardoSpectrum and Synplicity.
139 // The code correctly instantiates Altera EABs and Xilinx BlockRAMs.
142 reg [dw-1 :0] mem [(1<<aw) -1:0]; // instantiate memory
143 reg [dw-1:0] do; // data output registers
148 always@(posedge rclk)
149 if (rce) // clock enable instructs Xilinx tools to use SelectRAM (LUTS) instead of BlockRAM
153 always@(posedge rclk)
157 always@(posedge wclk)
165 // Instantiation of FPGA memory:
167 // Virtex/Spartan2 BlockRAMs
169 xilinx_ram_dp xilinx_ram(
190 xilinx_ram.dwidth = dw,
191 xilinx_ram.awidth = aw;
197 // Instantiation of FPGA memory:
199 // Altera FLEX/APEX EABs
201 altera_ram_dp altera_ram(
217 altera_ram.dwidth = dw,
218 altera_ram.awidth = aw;
222 `ifdef VENDOR_ARTISAN
225 // Instantiation of ASIC memory:
227 // Artisan Synchronous Double-Port RAM (ra2sh)
229 art_hsdp #(dw, 1<<aw, aw) artisan_sdp(
254 // Instantiation of ASIC memory:
256 // Avant! Asynchronous Two-Port RAM
275 // Instantiation of ASIC memory:
277 // Virage Synchronous 2-port R/W RAM
279 virage_stp virage_stp(
302 // Generic dual-port synchronous RAM model
306 // Generic RAM's registers and wires
308 reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
309 reg [dw-1:0] do_reg; // RAM data output register
312 // Data output drivers
314 assign do = (oe & rce) ? do_reg : {dw{1'bz}};
317 always @(posedge rclk)
319 do_reg <= #1 (we && (waddr==raddr)) ? {dw{1'b x}} : mem[raddr];
322 always @(posedge wclk)
327 // Task prints range of memory
328 // *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.
330 input [aw-1:0] start;
331 input [aw-1:0] finish;
334 for (rnum=start;rnum<=finish;rnum=rnum+1)
335 $display("Addr %h = %h",rnum,mem[rnum]);
339 `endif // !VENDOR_VIRAGE
340 `endif // !VENDOR_AVANT
341 `endif // !VENDOR_ARTISAN
342 `endif // !VENDOR_ALTERA
343 `endif // !VENDOR_XILINX
344 `endif // !VENDOR_FPGA
353 module altera_ram_dp(
362 q) /* synthesis black_box */;
364 parameter awidth = 7;
365 parameter dwidth = 8;
367 input [dwidth -1:0] data;
368 input [awidth -1:0] wraddress;
369 input [awidth -1:0] rdaddress;
375 output [dwidth -1:0] q;
377 // synopsis translate_off
378 // exemplar translate_off
390 .RdAddress(rdaddress),
397 .WrAddress(wraddress),
402 // exemplar translate_on
403 // synopsis translate_on
406 `endif // VENDOR_ALTERA
409 module xilinx_ram_dp (
423 DOB) /* synthesis black_box */ ;
425 parameter awidth = 7;
426 parameter dwidth = 8;
432 input [awidth-1:0] ADDRA;
433 input [dwidth-1:0] DIA;
435 output [dwidth-1:0] DOA;
441 input [awidth-1:0] ADDRB;
442 input [dwidth-1:0] DIB;
444 output [dwidth-1:0] DOB;
446 // insert simulation model
449 // synopsys translate_off
450 // exemplar translate_off
452 C_MEM_DP_BLOCK_V1_0 #(
499 // exemplar translate_on
500 // synopsys translate_on
503 `endif // VENDOR_XILINX