]> iEval git - clump.git/blob - lisp_processor.v
Add compiler
[clump.git] / lisp_processor.v
1 `include "gc.v"
2 `include "eval.v"
3 `include "reader.v"
4 `include "uart.v"
5 `include "writer.v"
6 `include "controller.v"
7
8 `define GCOP_NOP 4'd0
9 `define GCOP_CDR 4'd1
10 `define GCOP_CAR 4'd2
11 `define GCOP_CDRQ 4'd3
12 `define GCOP_CARQ 4'd4
13 `define GCOP_CARR 4'd5
14 `define GCOP_CDRRX 4'd6
15 `define GCOP_CARRX 4'd7
16 `define GCOP_CDRQX 4'd8
17 `define GCOP_CONS 4'd9
18 `define GCOP_XCONS 4'd10
19 `define GCOP_RPLACDR 4'd11
20 `define GCOP_LDQ 4'd12
21 `define GCOP_RDQ 4'd13
22 `define GCOP_RDQA 4'd14
23 `define GCOP_RDQCDRRX 4'd15
24
25 `ifdef SIM
26 `define UART_DIVIDE 1
27 `else
28 `define UART_DIVIDE 625
29 `endif
30
31 module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx);
32 wire [12:0] P;
33 wire [15:0] E1;
34 wire [15:0] E2;
35 wire [3:0] gcop;
36 wire [5:0] gostate;
37 wire [5:0] eostate;
38 wire conn_ea;
39 wire conn_et;
40
41 wire step_eval;
42
43 wire gc_ram_we;
44 wire [12:0] gc_ram_addr;
45 wire [15:0] gc_ram_di;
46
47 wire reader_ram_we;
48 wire [12:0] reader_ram_addr;
49 wire [15:0] reader_ram_di;
50
51 wire [12:0] writer_ram_addr;
52
53 wire ram_we;
54 wire [12:0] ram_addr;
55 wire [15:0] ram_di;
56 wire [15:0] ram_do;
57
58 wire eval_finished;
59 wire reader_finished;
60 wire writer_finished;
61
62 wire gc_clock_enable;
63 wire eval_clock_enable;
64 wire reader_clock_enable;
65 wire writer_clock_enable;
66 wire reset;
67
68 CTRL ctrl (.clk(clk), .step_eval(step_eval), .reader_finished(reader_finished), .eval_finished(eval_finished), .writer_finished(writer_finished), .gc_clock_enable(gc_clock_enable), .eval_clock_enable(eval_clock_enable), .reader_clock_enable(reader_clock_enable), .writer_clock_enable(writer_clock_enable), .reset(reset), .gc_ram_we(gc_ram_we), .reader_ram_we(reader_ram_we), .gc_ram_addr(gc_ram_addr), .reader_ram_addr(reader_ram_addr), .writer_ram_addr(writer_ram_addr), .gc_ram_di(gc_ram_di), .reader_ram_di(reader_ram_di), .ram_we(ram_we), .ram_addr(ram_addr), .ram_di(ram_di), .uart_is_receiving(uart_is_receiving), .uart_is_transmitting(uart_is_transmitting), .led(led));
69
70 GCRAM gcram (.clk(clk), .we(ram_we), .addr(ram_addr), .di(ram_di), .do(ram_do));
71
72 GC gc (.clk(clk), .rst(reset), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(gc_ram_we), .ram_addr(gc_ram_addr), .ram_di(gc_ram_di), .ram_do(ram_do), .Pout(P));
73
74 EVAL eval (.clk(clk), .rst(reset), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et), .eval_finished(eval_finished));
75
76 READER reader (.clk(clk), .clk_enable(reader_clock_enable), .rx_byte(uart_rx_byte), .rx_signal(uart_rx_signal), .finished(reader_finished), .ram_we(reader_ram_we), .ram_addr(reader_ram_addr), .ram_di(reader_ram_di));
77
78 WRITER writer (.clk(clk), .clk_enable(writer_clock_enable), .tx_byte(uart_tx_byte), .tx_signal(uart_tx_signal), .tx_busy(uart_is_transmitting), .finished(writer_finished), .ram_addr(writer_ram_addr), .ram_do(ram_do), .P(P));
79
80 // UART outputs
81 wire uart_rx_signal;
82 wire [7:0] uart_rx_byte;
83 wire uart_is_receiving;
84 wire uart_is_transmitting;
85 wire uart_rx_error;
86
87 // UART logic
88 wire uart_tx_signal;
89 wire [7:0] uart_tx_byte;
90
91 // 4800 baud uart
92 uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error));
93 endmodule
This page took 0.048206 seconds and 5 git commands to generate.