6 `include "controller.v"
11 `define GCOP_CDRQ 4'd3
12 `define GCOP_CARQ 4'd4
13 `define GCOP_CARR 4'd5
14 `define GCOP_CDRRX 4'd6
15 `define GCOP_CARRX 4'd7
16 `define GCOP_CDRQX 4'd8
17 `define GCOP_CONS 4'd9
18 `define GCOP_XCONS 4'd10
19 `define GCOP_RPLACDR 4'd11
20 `define GCOP_LDQ 4'd12
21 `define GCOP_RDQ 4'd13
22 `define GCOP_RDQA 4'd14
23 `define GCOP_RDQCDRRX 4'd15
28 `define UART_DIVIDE 625
31 module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx);
44 wire [12:0] gc_ram_addr;
45 wire [15:0] gc_ram_di;
48 wire [12:0] reader_ram_addr;
49 wire [15:0] reader_ram_di;
51 wire [12:0] writer_ram_addr;
63 wire eval_clock_enable;
64 wire reader_clock_enable;
65 wire writer_clock_enable;
68 CTRL ctrl (.clk(clk), .step_eval(step_eval), .reader_finished(reader_finished), .eval_finished(eval_finished), .writer_finished(writer_finished), .gc_clock_enable(gc_clock_enable), .eval_clock_enable(eval_clock_enable), .reader_clock_enable(reader_clock_enable), .writer_clock_enable(writer_clock_enable), .reset(reset), .gc_ram_we(gc_ram_we), .reader_ram_we(reader_ram_we), .gc_ram_addr(gc_ram_addr), .reader_ram_addr(reader_ram_addr), .writer_ram_addr(writer_ram_addr), .gc_ram_di(gc_ram_di), .reader_ram_di(reader_ram_di), .ram_we(ram_we), .ram_addr(ram_addr), .ram_di(ram_di), .uart_is_receiving(uart_is_receiving), .uart_is_transmitting(uart_is_transmitting), .led(led));
70 GCRAM gcram (.clk(clk), .we(ram_we), .addr(ram_addr), .di(ram_di), .do(ram_do));
72 GC gc (.clk(clk), .rst(reset), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(gc_ram_we), .ram_addr(gc_ram_addr), .ram_di(gc_ram_di), .ram_do(ram_do), .Pout(P));
74 EVAL eval (.clk(clk), .rst(reset), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et), .eval_finished(eval_finished));
76 READER reader (.clk(clk), .clk_enable(reader_clock_enable), .rx_byte(uart_rx_byte), .rx_signal(uart_rx_signal), .finished(reader_finished), .ram_we(reader_ram_we), .ram_addr(reader_ram_addr), .ram_di(reader_ram_di));
78 WRITER writer (.clk(clk), .clk_enable(writer_clock_enable), .tx_byte(uart_tx_byte), .tx_signal(uart_tx_signal), .tx_busy(uart_is_transmitting), .finished(writer_finished), .ram_addr(writer_ram_addr), .ram_do(ram_do), .P(P));
82 wire [7:0] uart_rx_byte;
83 wire uart_is_receiving;
84 wire uart_is_transmitting;
89 wire [7:0] uart_tx_byte;
92 uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error));