master_rom.v

   1 // ROM module with single input addr, output port, and clock input.
   2 // Data is clocked out of the ROM on positive clock edges.
   3
   4 module master_rom (input clk, input [7:0] addr, output reg [31:0] data);
   5    reg [31:0] rom [0:255];
   6    initial $readmemh("code.hex", rom);
   7
   8    always @ (posedge clk) begin
   9           data <= rom[addr];
  10    end
  11 endmodule