1 // Take variable duration pulse which may be high at any time and generate multiple cycle
2 // high pulses alligned with the positive edge of the clock pulse.
4 module MULTIPLE_TRIGGER #(parameter BITS = 4) (input clk, input trigger_in, output[BITS-1:0] trigger_out);
6 reg [BITS-1:0] trigger = 0;
8 reg last_trigger_in = 0;
10 always @ (posedge clk) begin
12 trigger <= { trigger[BITS-2:0], (!last_trigger_in & trigger_in) };
14 last_trigger_in <= trigger_in;
18 assign trigger_out = trigger;