4 * This Verilog module was generated automatically
5 * using the icepll tool from the IceStorm project.
6 * Use at your own risk.
8 * Given input frequency: 12.000 MHz
9 * Requested output frequency: 48.000 MHz
10 * Achieved output frequency: 48.000 MHz
20 .FEEDBACK_PATH("SIMPLE"),
21 .DIVR(4'b0000), // DIVR = 0
22 .DIVF(7'b0111111), // DIVF = 63
23 .DIVQ(3'b100), // DIVQ = 4
24 .FILTER_RANGE(3'b001) // FILTER_RANGE = 1
29 .REFERENCECLK(clock_in),
30 .PLLOUTCORE(clock_out)