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1 // ROM module with single input addr, output port, and clock input.
2 // Data is clocked out of the ROM on positive clock edges.
3
4 module ROM (input clk, input [3:0] addr, output reg [7:0] data);
5 always @ (posedge clk) begin
6 case(addr)
7 4'd0: data <= 8'b0001_0110; // LDI 6
8 4'd1: data <= 8'b0110_1001; // JP 9
9 4'd2: data <= 8'b0010_0001; // ADD 1
10 4'd3: data <= 8'b1001_0000; // WRITE
11 4'd4: data <= 8'b0110_0010; // JP 2
12 4'd5: data <= 8'b0000_0000;
13 4'd6: data <= 8'b0001_0001; // LDI 1
14 4'd7: data <= 8'b1000_0000; // READ
15 4'd8: data <= 8'b0110_0111; // JP 7
16 4'd9: data <= 8'b1110_0000; // LDQ
17 4'd10: data <= 8'b0001_1100; // LDI 12
18 4'd11: data <= 8'b1010_0000; // CONS
19 4'd12: data <= 8'b1100_0000; // RDQ
20 4'd13: data <= 8'b1101_0000; // CDR
21 4'd14: data <= 8'b1100_0000; // RDQ
22 4'd15: data <= 8'b0000_0000;
23 default: data <= 8'bxxxx_xxxx;
24 endcase
25 end
26
27 assign out_data = data_out_reg;
28 endmodule
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