1 // Take variable duration pulse which may be high at any time and generate a single cycle
2 // high pulse alligned with the positive edge of the clock pulse.
4 module SINGLE_TRIGGER (input clk, input trigger_in, output trigger_out);
8 reg last_trigger_in = 0;
10 always @ (posedge clk) begin
12 if (!last_trigger_in & trigger_in)
17 last_trigger_in <= trigger_in;
21 assign trigger_out = trigger;