1 `define STATE_WRITE_TYPE 3'd0
2 `define STATE_WRITE1 3'd1
3 `define STATE_WRITE2 3'd2
4 `define STATE_WRITE3 3'd3
5 `define STATE_WRITE4 3'd4
7 module WRITER (input clk, input clk_enable, output [7:0] uart_tx_byte, output reg uart_tx_signal = 0, input uart_is_transmitting, output reg finished = 0, input [15:0] result);
8 reg [2:0] state = `STATE_WRITE_TYPE;
11 hex_to_ascii h2a (.hex(tx_hex), .ascii(uart_tx_byte));
13 always @ (posedge clk)
19 `STATE_WRITE_TYPE: begin
21 if(!uart_is_transmitting && !uart_tx_signal) begin
23 tx_hex <= {1'b0, result[15:13]};
24 state <= `STATE_WRITE1;
29 if(!uart_is_transmitting && !uart_tx_signal) begin
31 tx_hex <= {3'b0, result[12]};
32 state <= `STATE_WRITE2;
37 if(!uart_is_transmitting && !uart_tx_signal) begin
39 tx_hex <= result[11:8];
40 state <= `STATE_WRITE3;
45 if(!uart_is_transmitting && !uart_tx_signal) begin
47 tx_hex <= result[7:4];
48 state <= `STATE_WRITE4;
53 if(!uart_is_transmitting && !uart_tx_signal) begin
55 tx_hex <= result[3:0];
57 state <= `STATE_WRITE_TYPE;