1 `define STATE_START 2'b00
2 `define STATE_WRITE1 2'b01
3 `define STATE_WRITE2 2'b10
4 `define STATE_INCREMENT 2'b11
6 module WRITER (input clk, input clk_enable, output reg [7:0] uart_tx_byte, output reg uart_tx_signal = 0, input uart_is_transmitting, output reg finished = 0, output [12:0] ram_addr, input [15:0] ram_do, input [12:0] P);
7 reg [1:0] state = `STATE_START;
9 reg [12:0] current_index;
12 assign ram_addr = current_index;
14 always @ (posedge clk) begin
24 state <= `STATE_WRITE1;
28 if(!uart_is_transmitting && !uart_tx_signal) begin
30 uart_tx_byte <= ram_do[15:8];
31 state <= `STATE_WRITE2;
36 if(!uart_is_transmitting && !uart_tx_signal) begin
38 uart_tx_byte <= ram_do[7:0];
39 state <= `STATE_INCREMENT;
43 `STATE_INCREMENT: begin
44 current_index <= current_index + 1;
45 if(current_index >= freeptr) begin
47 state <= `STATE_START;
49 state <= `STATE_WRITE1;
52 endcase // case (state)
53 end // if (clk_enable)